scholarly journals Implementation of an LDPC decoder for IEEE 802.11n using VivadoTM High-Level Synthesis

2021 ◽  
Vol 8 ◽  
pp. 1-4
Author(s):  
Ernest Scheiber ◽  
Guido H. Bruck ◽  
Peter Jung
Keyword(s):  
Forward Error Correction ◽  
Implementation Process ◽  
Research Topic ◽  
High Level Synthesis ◽  
Ldpc Decoder ◽  
The Past ◽  
High Level ◽  
Forward Error ◽  
Hardware Designs ◽  
High Processing

The increasing complexity of hardware designs calls for design methodolgies that use more abstract design entries and increased automation of the implementation process. Highlevel synthesis (HLS) has been a research topic for the past 20 years, and current tools, such as Xilinx VivadoTM HLS promise to bring HLS to widespread use. In this paper we use Xilinx VivadoTMHLS to design an LDPC decoder for 802.11n. Forward error correction decoders are typically implemented in hardware due to the high processing requirements and therefore an LDPC decoder is an appropriate example to demonstrate the power of high-level synthesis

scholarly journals FPGA-Oriented LDPC Decoder for Cyber-Physical Systems

Mathematics ◽  
2020 ◽  
Vol 8 (5) ◽  
pp. 723 ◽  
Author(s):  
Mateusz Kuc ◽  
Wojciech Sułek ◽  
Dariusz Kania
Keyword(s):  
Forward Error Correction ◽  
Broad Class ◽  
Experimental Studies ◽  
Cyber Physical Systems ◽  
Coding System ◽  
Physical Systems ◽  
Testing Environment ◽  
Ldpc Decoder ◽  
Coding Systems ◽  
Forward Error

A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of decoders with different bit-lengths of data (beliefs that are messages propagated between computing units) is also provided. The presented decoder has been implemented with a distributed control system. Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems.

scholarly journals High Level Synthesis FPGA Implementation of the Jacobi Algorithm to Solve the Eigen Problem

2015 ◽  
Vol 2015 ◽  
pp. 1-11 ◽  
Author(s):  
Ignacio Bravo ◽  
César Vázquez ◽  
Alfredo Gardel ◽  
José L. Lázaro ◽  
Esther Palomar
Keyword(s):  
High Level Synthesis ◽  
Eigenvalue Decomposition ◽  
Real Time Processing ◽  
Low Level ◽  
Hardware Implementations ◽  
Jacobi Algorithm ◽  
Field Programmable ◽  
Hardware Architectures ◽  
High Level ◽  
Hardware Designs

We present a hardware implementation of the Jacobi algorithm to compute the eigenvalue decomposition (EVD). The computation of eigenvalues and eigenvectors has many applications where real time processing is required, and thus hardware implementations are often mandatory. Some of these implementations have been carried out with field programmable gate array (FPGA) devices using low level register transfer level (RTL) languages. In the present study, we used the Xilinx Vivado HLS tool to develop a high level synthesis (HLS) design and evaluated different hardware architectures. After analyzing the design for different input matrix sizes and various hardware configurations, we compared it with the results of other studies reported in the literature, concluding that although resource usage may be higher when HLS tools are used, the design performance is equal to or better than low level hardware designs.

scholarly journals Formal verification of high-level synthesis

2021 ◽  
Vol 5 (OOPSLA) ◽  
pp. 1-30
Author(s):  
Yann Herklotz ◽  
James D. Pollard ◽  
Nadesh Ramanathan ◽  
John Wickerson
Keyword(s):  
Control Flow ◽  
High Level Synthesis ◽  
Function Calls ◽  
Comparable Performance ◽  
Order Of Magnitude ◽  
Hardware Description ◽  
The Rich ◽  
High Level ◽  
Hardware Designs ◽  
Application Specific

High-level synthesis (HLS), which refers to the automatic compilation of software into hardware, is rapidly gaining popularity. In a world increasingly reliant on application-specific hardware accelerators, HLS promises hardware designs of comparable performance and energy efficiency to those coded by hand in a hardware description language such as Verilog, while maintaining the convenience and the rich ecosystem of software development. However, current HLS tools cannot always guarantee that the hardware designs they produce are equivalent to the software they were given, thus undermining any reasoning conducted at the software level. Furthermore, there is mounting evidence that existing HLS tools are quite unreliable, sometimes generating wrong hardware or crashing when given valid inputs. To address this problem, we present the first HLS tool that is mechanically verified to preserve the behaviour of its input software. Our tool, called Vericert, extends the CompCert verified C compiler with a new hardware-oriented intermediate language and a Verilog back end, and has been proven correct in Coq. Vericert supports most C constructs, including all integer operations, function calls, local arrays, structs, unions, and general control-flow statements. An evaluation on the PolyBench/C benchmark suite indicates that Vericert generates hardware that is around an order of magnitude slower (only around 2× slower in the absence of division) and about the same size as hardware generated by an existing, optimising (but unverified) HLS tool.

scholarly journals A VLSI Design for the LTE Turbo Decoder

2012 ◽  
Vol 7 (1) ◽  
pp. 16-22
Author(s):  
Ilan Schnitman Souza ◽  
V. T. Dos Reis
Keyword(s):  
Turbo Codes ◽  
High Performance ◽  
Forward Error Correction ◽  
Vlsi Design ◽  
Turbo Decoder ◽  
Wireless Telecommunications ◽  
And Performance ◽  
Window Approach ◽  
High Level ◽  
Forward Error

Due to the need of high performance, new wireless telecommunications standards such asWIMAX and LTE are using turbo-codes as a forward error correction (FEC) choice.This design targets either a self-contained IP (Intellectual Property) or integration into the physical layer project. This work presents all steps for the implementation of an LTE standard turbo decoder: from algorithm modeling in high level programming language to architecture using a sliding window approach seeking throughput needed, getting into physical implementation at TSMC 65nm. Each aspect of the specification and performance were analyzed in their proper stages.

scholarly journals Extending C++ for Heterogeneous Quantum-Classical Computing

2021 ◽  
Vol 2 (2) ◽  
pp. 1-36
Author(s):  
Alexander Mccaskey ◽  
Thien Nguyen ◽  
Anthony Santana ◽  
Daniel Claudino ◽  
Tyler Kharazi ◽  
...  
Keyword(s):  
Forward Error Correction ◽  
Quantum Algorithm ◽  
System Level ◽  
Circuit Optimization ◽  
Language Extension ◽  
Quantum Programming ◽  
Near Term ◽  
Classical Computing ◽  
High Level ◽  
Forward Error

We present qcor—a language extension to C++ and compiler implementation that enables heterogeneous quantum-classical programming, compilation, and execution in a single-source context. Our work provides a first-of-its-kind C++ compiler enabling high-level quantum kernel (function) expression in a quantum-language agnostic manner, as well as a hardware-agnostic, retargetable compiler workflow targeting a number of physical and virtual quantum computing backends. qcor leverages novel Clang plugin interfaces and builds upon the XACC system-level quantum programming framework to provide a state-of-the-art integration mechanism for quantum-classical compilation that leverages the best from the community at-large. qcor translates quantum kernels ultimately to the XACC intermediate representation, and provides user-extensible hooks for quantum compilation routines like circuit optimization, analysis, and placement. This work details the overall architecture and compiler workflow for qcor, and provides a number of illuminating programming examples demonstrating its utility for near-term variational tasks, quantum algorithm expression, and feed-forward error correction schemes.

Machine Learning into Metaheuristics

2021 ◽  
Vol 54 (6) ◽  
pp. 1-32
Author(s):  
El-Ghazali Talbi
Keyword(s):  
Machine Learning ◽  
Optimization Problem ◽  
State Of The Art ◽  
Research Topic ◽  
High Quality ◽  
Research Issues ◽  
The Past ◽  
Open Research ◽  
Comprehensive Survey ◽  
High Level

During the past few years, research in applying machine learning (ML) to design efficient, effective, and robust metaheuristics has become increasingly popular. Many of those machine learning-supported metaheuristics have generated high-quality results and represent state-of-the-art optimization algorithms. Although various appproaches have been proposed, there is a lack of a comprehensive survey and taxonomy on this research topic. In this article, we will investigate different opportunities for using ML into metaheuristics. We define uniformly the various ways synergies that might be achieved. A detailed taxonomy is proposed according to the concerned search component: target optimization problem and low-level and high-level components of metaheuristics. Our goal is also to motivate researchers in optimization to include ideas from ML into metaheuristics. We identify some open research issues in this topic that need further in-depth investigations.

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