ICCAD-2020 CAD contest in X-value equivalence checking and benchmark suite

2020 ◽  
Author(s):  
Chih-Jen (Jacky) Hsu ◽  
Chi-An (Rocky) Wu ◽  
Ching-Yi Huang ◽  
Kei-Yong Khoo
Keyword(s):  
Equivalence Checking ◽  
Benchmark Suite

Adding a Reproducible Airplane Model to the Austin RCS Benchmark Suite

2020 ◽  
Author(s):  
Jon T. Kelley ◽  
Andrew Maicke ◽  
David A. Chamulak ◽  
Clifton C. Courtney ◽  
Ali E. Yilmaz
Keyword(s):  
Benchmark Suite

iMLBench: A Machine Learning Benchmark Suite for CPU-GPU Integrated Architectures

2020 ◽  
pp. 1-1
Author(s):  
Chenyang Zhang ◽  
Feng Zhang ◽  
Xiaoguang Guo ◽  
Bingsheng He ◽  
Xiao Zhang ◽  
...  
Keyword(s):  
Machine Learning ◽  
Benchmark Suite

A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor Cores

2021 ◽  
Author(s):  
Aleksa Damljanovic ◽  
Annachiara Ruospo ◽  
Ernesto Sanchez ◽  
Giovanni Squillero
Keyword(s):  
Hardware Trojans ◽  
Benchmark Suite

scholarly journals A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures

2020 ◽  
Vol 17 (4) ◽  
pp. 1-30
Author(s):  
Cristóbal Ramírez ◽  
César Alejandro Hernández ◽  
Oscar Palomar ◽  
Osman Unsal ◽  
Marco Antonio Ramírez ◽  
...  
Keyword(s):  
Benchmark Suite ◽  
Vector Architectures

A Sparse Tensor Benchmark Suite for CPUs and GPUs

2020 ◽  
Author(s):  
Jiajia Li ◽  
Mahesh Lakshminarasimhan ◽  
Xiaolong Wu ◽  
Ang Li ◽  
Catherine Olschanowsky ◽  
...  
Keyword(s):  
Benchmark Suite

Performance, Power, and Energy-Efficiency Impact Analysis of Compiler Optimizations on the SPEC CPU 2017 Benchmark Suite

2020 ◽  
Author(s):  
Norbert Schmitt ◽  
James Bucek ◽  
John Beckett ◽  
Aaron Cragin ◽  
Klaus-Dieter Lange ◽  
...  
Keyword(s):  
Energy Efficiency ◽  
Impact Analysis ◽  
Compiler Optimizations ◽  
Benchmark Suite ◽  
Power And Energy

scholarly journals Thread-Aware Mechanism to Enhance Inter-Node Load Balancing for Multithreaded Applications on NUMA Systems

2021 ◽  
Vol 11 (14) ◽  
pp. 6486
Author(s):  
Mei-Ling Chiang ◽  
Wei-Lun Su
Keyword(s):  
Load Balancing ◽  
Critical Path ◽  
Selection Procedure ◽  
Remote Memory ◽  
Data Mapping ◽  
Linux Kernel ◽  
Access Memory ◽  
Selection Policy ◽  
Benchmark Suite ◽  
Thread Mapping

NUMA multi-core systems divide system resources into several nodes. When an imbalance in the load between cores occurs, the kernel scheduler’s load balancing mechanism then migrates threads between cores or across NUMA nodes. Remote memory access is required for a thread to access memory on the previous node, which degrades performance. Threads to be migrated must be selected effectively and efficiently since the related operations run in the critical path of the kernel scheduler. This study focuses on improving inter-node load balancing for multithreaded applications. We propose a thread-aware selection policy that considers the distribution of threads on nodes for each thread group while migrating one thread for inter-node load balancing. The thread is selected for which its thread group has the least exclusive thread distribution, and thread members are distributed more evenly on nodes. This has less influence on data mapping and thread mapping for the thread group. We further devise several enhancements to eliminate superfluous evaluations for multithreaded processes, so the selection procedure is more efficient. The experimental results for the commonly used PARSEC 3.0 benchmark suite show that the modified Linux kernel with the proposed selection policy increases performance by 10.7% compared with the unmodified Linux kernel.

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