A dual mode self-test for a stand alone AES core

Advanced Encryption Standard (AES) is the most secured ciphertext algorithm that is unbreakable in a software platform’s reasonable time. AES has been proved to be the most robust symmetric encryption algorithm declared by the USA Government. Its hardware implementation offers much higher speed and physical security than that of its software implementation. The testability and hardware Trojans are two significant concerns that make the AES chip complex and vulnerable. The problem of testability in the complex AES chip is not addressed yet, and also, the hardware Trojan insertion into the chip may be a significant security threat by leaking information to the intruder. The proposed method is a dual-mode self-test architecture that can detect the hardware Trojans at the manufacturing test and perform an online parametric test to identify parametric chip defects. This work contributes to partitioning the AES circuit into small blocks and comparing adjacent blocks to ensure self-referencing. The detection accuracy is sharpened by a comparative power ratio threshold, determined by process variations and the accuracy of the built-in current sensors. This architecture can reduce the delay, power consumption, and area overhead compared to other works.

Prognostics and Secure Health Management (PSHM) of Electronic Systems in Zero-Trust Environment

The Prognostics and Health Management (PHM) of electronic systems has reached high levels of maturity, with both generic and system-specific PHM techniques available. While these techniques are able to detect naturally occurring faults and predict their impact on the system lifetime, they might not be able to do so if the faults are maliciously induced. Maliciously induced faults could be due to hardware threats; i.e., electronic products that are recycled, remarked, defective, cloned, or tampered (through the insertion of hardware trojans). Increased outsourcing in the fabrication of electronic products has made them susceptible to the insertion of hardware threats in untrusted manufacturing facilities. In many cases, hardware threats are more destructive than software ones as they cannot be remedied by a software patch and are difficult to remove. Hardware threats can cause undesired system behavior such as information leakage, functional failure, maliciously induced aging, etc. The proliferation of hardware threats could outpace the implementation of their detection mechanisms. This might lead to a scenario where all products manufactured by untrusted manufacturing facilities are suspect until verified otherwise. This has parallels to Zero-Trust Architecture, a network security concept developed to help prevent data breaches by removing the notion of trust from an organization's network architecture. To extend the concept of Zero-Trust Architecture from the network to the hardware domain and to ensure hardware security, a paradigm shift from PHM to PSHM (Prognostics and Secure Health Management) is needed. This paper lays out a compelling case for the need for this shift and how the PHM community can adapt its research to ensure the safe, reliable, and secure operation of systems in this challenging new environment.

A Deep Learning Approach in Optical Inspection to Detect Hidden Hardware Trojans and Secure Cybersecurity in Electronics Manufacturing Supply Chains

Deep learning methods have been extensively studied and have been proven to be very useful in multiple fields of technology. This paper presents a deep learning approach to optically detect hidden hardware trojans in the manufacturing and assembly phase of printed circuit boards to secure electronic supply chains. Trojans can serve as backdoors of accessing on chip data, can potentially alter functioning and in some cases may even deny intended service of the chip. Apart from consumer electronics, printed circuit boards are used in mission critical applications like military and space equipment. Security compromise or data theft can have severe impact and thus demand research attention. The advantage of the proposed method is that it can be implemented in a manufacturing environment with limited training data. It can also provide better coverage in detection of hardware trojans over traditional methods. Image recognition algorithms need to have deeper penetration inside the training layers for recognizing physical variations of image patches. However, traditional network architectures often face vanishing gradient problem when the network layers are added. This hampers the overall accuracy of the network. To solve this a Residual network with multiple layers is used in this article. The ResNet34 algorithm can identify manufacturing tolerances and can differentiate between a manufacturing defect and a hardware trojan. The ResNet operates on the fundamental principle of learning from the residual of the output of preceding layer. In the degradation issue, it is observed that, a shallower network performs better than deeper network. However, this is with the downside of lower accuracy. Thus, a skip connection is made to provide an alternative path for the gradient to skip forward the training of few layers and add in multiple repeating blocks to achieve higher accuracy and lower training times. Implementation of this method can bolster automated optical inspection setup used to detect manufacturing variances on a printed circuit board. The results show a 98.5% accuracy in optically detecting trojans by this method and can help cut down redundancy of physically testing each board. The research results also provide a new consideration of hardware trojan benchmarking and its effect on optical detection.