This paper presents a performance-oriented placement and routing tool for field-programmable
gate arrays. Using recursive geometric partitioning for simultaneous
placement and global routing, and a graph-based strategy for detailed routing, our tool
optimizes source-sink pathlengths, channel width and total wirelength. Our results
compare favorably with other FPGA layout tools, as measured by the maximum
channel width required to place and route several benchmarks.
A geometric partitioning method for distributed tomographic reconstruction
