Detailed Placement and Global Routing Co-optimization with Complex Constraints

With several divided stages, placement and routing are the most critical and challenging steps in VLSI physical design. To ensure that physical implementation problems can be manageable and converged in a reasonable runtime, placement/routing problems are usually further split into several sub-problems, which may cause conservative margin reservation and mis-correlation. Therefore, it is desirable to design an algorithm that can accurately and efficiently consider placement and routing simultaneously. In this paper, we propose a detailed placement and global routing co-optimization algorithm while considering complex routing constraints to avoid conservative margin reservation and mis-correlation in placement/routing stages. Firstly, we present a rapidly preprocessing technology based on R-tree to improve the initial routing results. After that, a BFS-based approximate optimal addressing algorithm in 3D is designed to find a proper destination for cell movement. We propose an optimal region selection algorithm based on the partial routing solution to jump out of the local optimal solution. Further, a fast partial net rip-up and rerouted algorithm is used in the process of cell movement. Finally, we adopt an efficient refinement technique to reduce the routing length further. Compared with the top 3 winners according to the 2020 ICCAD CAD contest benchmarks, the experimental results show that our algorithm achieves the best routing length reduction for all cases with a shorter runtime. On average, our algorithm can improve 0.7%, 1.5%, and 1.7% for the first, second, and third place, respectively. In addition, we can still obtain the best results after relaxing the maximum cell movement constraint, which further illustrates the effectiveness of our algorithm.

A High Performance Global Routing Algorithm on Julia Parallel Computing Platform

o keep pace with the design requirements of Integrated Circuits (ICs), parallel processing is adopted. The path to be routed between two nodes may or may not be dependent on the previously routed paths. The solution requires careful attention in distributing the nets to be routed to different processors. Previous work on allocating the tasks to processors has been quite successful, reporting upto 3x improvement on 4 cores and 5x improvement on 8 core machine. The advantage of increasing the number of cores diminishes with each added processor and the challenge lies in being able to maintain the improvement per added core. The existing techniques of distributing the nets cannot provide additional advantage of using more than 8 cores. This paper improves the work on parallelizing global routing using a technique of balancing the load on the processors for better utilization of the resources. A relatively new budding platform Julia has been used which provides the ease of programming while maintaining the performance of the C language. Technique used in this paper has enabled to use 16 cores with routing solutions obtained in 0.8 minutes achieving 12.5 times speedup compared to sequential processing on a single core

Wire length optimization of VLSI circuits using IWO algorithm and its hybrid

Purpose Advancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die where global routing problem remains significant with a trade-off of power dissipation and interconnect delay. This paper aims to solve the increased complexity in VLSI chip by minimization of the wire length in VLSI circuits using a new approach based on nature-inspired meta-heuristic, invasive weed optimization (IWO). Further, this paper aims to achieve maximum circuit optimization using IWO hybridized with particle swarm optimization (PSO). Design/methodology/approach This paper projects the complexities of global routing process of VLSI circuit design in mapping it with a well-known NP-complete problem, the minimum rectilinear Steiner tree (MRST) problem. IWO meta-heuristic algorithm is proposed to meet the MRST problem more efficiently and thereby reducing the overall wire-length of interconnected nodes. Further, the proposed approach is hybridized with PSO, and a comparative analysis is performed with geosteiner 5.0.1 and existing PSO technique over minimization, consistency and convergence against available benchmark. Findings This paper provides high performance–enhanced IWO algorithm, which keeps in generating low MRST value, thereby successful wire length reduction of VLSI circuits is significantly achieved as evident from the experimental results as compared to PSO algorithm and also generates value nearer to geosteiner 5.0.1 benchmark. Even with big VLSI instances, hybrid IWO with PSO establishes its robustness over achieving improved optimization of overall wire length of VLSI circuits. Practical implications This paper includes implications in the areas of optimization of VLSI circuit design specifically in the arena of VLSI routing and the recent developments in routing optimization using meta-heuristic algorithms. Originality/value This paper fulfills an identified need to study optimization of VLSI circuits where minimization of overall interconnected wire length in global routing plays a significant role. Use of nature-based meta-heuristics in solving the global routing problem is projected to be an alternative approach other than conventional method.

Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles

As one of the most important routing problems in the complex network within a very-large-scale integration (VLSI) circuit, bus routing has become much more challenging when witnessing the advanced technology node enters the deep nanometer era because all bus bits need to be routed with the same routing topology in the context. In particular, the nonuniform routing track configuration and obstacles bring the largest difficulty for maintaining the same topology for all bus bits. In this paper, we first present a track handling technique to unify the nonuniform routing track configuration with obstacles. Then, we formulate the topology-aware single bus routing as an unsplittable flow problem (UFP), which is integrated into a negotiation-based global routing to determine the desired routing regions for each bus. A topology-aware track assignment is also presented to allocate the tracks to each segment of buses under the guidance of the global routing result. Finally, a detailed routing scheme is proposed to connect the segments of each bus. We evaluate our routing result with the benchmark suite of the 2018 CAD Contest. Compared with the top-3 state-of-the-art methods, experimental results show that our proposed algorithm achieves the best overall score regarding specified time limitations.

X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution

Global routing is an important link in very large scale integration (VLSI) design. As the best model of global routing, X-architecture Steiner minimal tree (XSMT) has a good performance in wire length optimization. XSMT belongs to non-Manhattan structural model, and its construction process cannot be completed in polynomial time, so the generation of XSMT is an NP hard problem. In this paper, an X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution (XSMT-MoDDE) is proposed. Firstly, an effective encoding strategy, a fitness function of XSMT, and an initialization strategy of population are proposed to record the structure of XSMT, evaluate the cost of XSMT and obtain better initial particles, respectively. Secondly, elite selection and cloning strategy, multiple mutation strategies, and adaptive learning factor strategy are presented to improve the search process of discrete differential evolution algorithm. Thirdly, an effective refining strategy is proposed to further improve the quality of the final Steiner tree. Finally, the results of the comparative experiments prove that XSMT-MoDDE can get the shortest wire length so far, and achieve a better optimization degree in the larger-scale problem.

Empirical Results of Forming an Effective Topology in the Internet Based on the Global Routing System Security Assessments

Вирішено актуальну науково-практичну проблему підвищення рівня захищеності топо­ло­гії глобальної комп'ютерної мережі Інтернет від кібератак на систему глобальної маршрутизації. Описано застосування методики пошуку ефективної топології міжмере­жевих зв'язків в Інтернеті для захисту від атак на систему глобальної маршрутизації, де критерієм ефективності топології є оцінка ризику як міра захищеності інформації. Наведено практичні результати застосування методики для різних за масштабом та геогра­фією суб’єктів глобальної маршрутизації. Візуалізований результат моделювання пока­зує практичні шляхи підвищення захищеності топології міжвузлових зв'язків від кібер­атак типу перехоплення маршруту.