scholarly journals Formal ESL Synthesis for Control-Intensive Applications

2012 ◽  
Vol 2012 ◽  
pp. 1-30 ◽  
Author(s):  
Michael F. Dossis
Keyword(s):  
Electronic System ◽  
System Level ◽  
Specific Design ◽  
Program Code ◽  
Electronic System Level ◽  
Executable Specifications ◽  
Real World Applications ◽  
High Level ◽  
Embedded Applications ◽  
Application Specific

Due to the massive complexity of contemporary embedded applications and integrated systems, long effort has been invested in high-level synthesis (HLS) and electronic system level (ESL) methodologies to automatically produce correct implementations from high-level, abstract, and executable specifications written in program code. If the HLS transformations that are applied on the source code are formal, then the generated implementation is correct-by-construction. The focus in this work is on application-specific design, which can deliver optimal, and customized implementations, as opposed to platform or IP-based design, which is bound by the limits and constraints of the preexisting architecture. This work surveys and reviews past and current research in the area of ESL and HLS. Then, a prototype HLS compiler tool that has been developed by the author is presented, which utilizes compiler-generators and logic programming to turn the synthesis into a formal process. The scheduler PARCS and the formal compilation of the system are tested with a number of benchmarks and real-world applications. This demonstrates the usability and applicability of the presented method.

A high-level requirements engineering methodology for electronic system-level design

2007 ◽  
Vol 33 (4) ◽  
pp. 249-268 ◽  
Author(s):  
N. Gorse ◽  
P. Bélanger ◽  
A. Chureau ◽  
E.M. Aboulhamid ◽  
Y. Savaria
Keyword(s):  
Requirements Engineering ◽  
Electronic System ◽  
System Level ◽  
System Level Design ◽  
Electronic System Level ◽  
Level Design ◽  
High Level

scholarly journals An Approach for Power Estimation at Electronic System Level using Distributed Simulation

2016 ◽  
Vol 11 (3) ◽  
pp. 159-170
Author(s):  
Helder F. A. Oliveira ◽  
Alisson V. Brito ◽  
Joseana M. F. R. Araujo ◽  
Elmar U. K. Melcher
Keyword(s):  
Distributed Simulation ◽  
Power Estimation ◽  
Electronic System ◽  
System Level ◽  
Multiprocessor System ◽  
High Level Architecture ◽  
Electronic System Level ◽  
On Chip ◽  
High Level ◽  
Abstraction Levels

The present research aims to develop an approach using HLA (High Level Architecture), enabling the cre-ation of a distributed and heterogeneous environment, composed by different tools and models to obtain a better trade-off between accuracy and run time in power estimation. These models can be described in different languages and/or abstraction levels, as well as use different power estimation approaches. The use of HLA enables the synchronized and distributed simulation of the elements that compose the simulation environment. The approach must allow the collecting and grouping of power estimation data in a centralized manner. As a case study, an MPSoC (MultiProcessor System-on-Chip) ESL/TLM model, described in C++/SystemC, and an ESL model, created on Ptolemy framework, have been used. The experimental results show the flexibility of the approach, which promotes an integrated view of power estimation data.

scholarly journals System Level Design of Reconfigurable Server Farms Using Elliptic Curve Cryptography Processor Engines

2014 ◽  
Vol 2014 ◽  
pp. 1-8
Author(s):  
Sangook Moon ◽  
Jongsu Park
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
Electronic System ◽  
Register Transfer Level ◽  
System Level ◽  
Simulation Environment ◽  
Robust Test ◽  
Level Of Abstraction ◽  
Electronic System Level ◽  
High Level

As today’s hardware architecture becomes more and more complicated, it is getting harder to modify or improve the microarchitecture of a design in register transfer level (RTL). Consequently, traditional methods we have used to develop a design are not capable of coping with complex designs. In this paper, we suggest a way of designing complex digital logic circuits with a soft and advanced type of SystemVerilog at an electronic system level. We apply the concept of design-and-reuse with a high level of abstraction to implement elliptic curve crypto-processor server farms. With the concept of the superior level of abstraction to the RTL used with the traditional HDL design, we successfully achieved the soft implementation of the crypto-processor server farms as well as robust test bench code with trivial effort in the same simulation environment. Otherwise, it could have required error-prone Verilog simulations for the hardware IPs and other time-consuming jobs such as C/SystemC verification for the software, sacrificing more time and effort. In the design of the elliptic curve cryptography processor engine, we propose a 3X faster GF(2m) serial multiplication architecture.

scholarly journals An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms

2011 ◽  
Vol 2011 ◽  
pp. 1-12 ◽  
Author(s):  
Abel G. Silva-Filho ◽  
Filipe R. Cordeiro ◽  
Cristiano C. Araújo ◽  
Adriano Sarmento ◽  
Millena Gomes ◽  
...  
Keyword(s):  
Energy Consumption ◽  
System Modeling ◽  
Electronic System ◽  
System Level ◽  
Energy Consumption Analysis ◽  
Electronic System Level ◽  
Architecture Exploration ◽  
Uml 2.0 ◽  
Complex Circuits ◽  
High Level

The design of complex circuits as SoCs presents two great challenges to designers. One is the speeding up of system functionality modeling and the second is the implementation of the system in an architecture that meets performance and power consumption requirements. Thus, developing new high-level specification mechanisms for the reduction of the design effort with automatic architecture exploration is a necessity. This paper proposes an Electronic-System-Level (ESL) approach for system modeling and cache energy consumption analysis of SoCs called PCacheEnergyAnalyzer. It uses as entry a high-level UML-2.0 profile model of the system and it generates a simulation model of a multicore platform that can be analyzed for cache tuning. PCacheEnergyAnalyzer performs static/dynamic energy consumption analysis of caches on platforms that may have different processors. Architecture exploration is achieved by letting designers choose different processors for platform generation and different mechanisms for cache optimization. PCacheEnergyAnalyzer has been validated with several applications of Mibench, Mediabench, and PowerStone benchmarks, and results show that it provides analysis with reduced simulation effort.

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