scholarly journals NULL Convention Floating Point Multiplier

2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Anitha Juliette Albert ◽  
Seshasayanan Ramachandran

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.

2002 ◽  
Vol 199 ◽  
pp. 506-507
Author(s):  
Carlo Rosolen ◽  
Alain Lecacheux ◽  
Eric Gerard ◽  
Vincent Clerc ◽  
Laurent Denis

Radio astronomy in the decameter to centimeter wavelength range is facing new challenges because of man made interferences due to increasing needs in telecommunications. At the Radioastronomy department of Paris Meudon Observatory, we have been working since four years on high dynamic range digital receivers based on Digital Signal Processors (DSP). The first achievement is a digital spectro- polarimeter devoted to spectroscopy of astrophysical radiation in decameter range, now in operation at the Nancay Decameter array. The block diagram of the receiver includes a high dynamic range analogue section followed by a 12 bits analogue to digital converter. The digital part makes use of high power, programmable digital circuits for signal processing, arranged in a dedicated parallel architecture, able to compute in real time the power spectrum and the correlation of the input signals. This receiver was also used, as spectrometer backend, at Nancay decimetric radiotelescope and has performed very well in the presence of very strong interferences. We are presently working on a new digital receiver with broader bandwidth. The objective is 2 × 25 MHz band with at least 60 dB dynamic range. This new receiver will use additional computation power in order to recognise and avoid man made interferences which corrupt the radio astronomical signal. At the Nancay Radioastronomy Observatory, we have started to develop a new digital configurable receiver with 8 times 25 MHz band and ten thousand channels. For low frequency radioastronomy, direct spectrum computation technique is really powerful and offers new capabilities for real time interferences excision. Fig. 1 shows pulsar observations in the presence of interference made with the DSP receiver on the UTR-2 radiotelescope. Fig. 2 shows the effect of satellite interfernce on OH observations made with the Nancay telescope. Fig. 3 shows the block diagram of the DSP system and demonstrates how offline excision of interference in the frequency time-domain enables recovery of the signal. The final spectrum had 960 minutes integration on and off source and took 8045 minutes of procession on a 450 MHz Pentium II.


1991 ◽  
Author(s):  
Herve C. Lefevre ◽  
Philippe Martin ◽  
J. Morisse ◽  
Pascal Simonpietri ◽  
P. Vivenot ◽  
...  

Currently, each CPU has one or additional Floating Point Units (FPUs) integrated inside it. It is usually utilized in math wide-ranging applications, such as digital signal processing. It is found in places be established in engineering, medical and military fields in adding along to in different fields requiring audio, image or video handling. A high-speed and energy-efficient floating point unit is naturally needed in the electronics diligence as an arithmetic unit in microprocessors. The most operations accounting 95% of conformist FPU are multiplication and addition. Many applications need the speedy execution of arithmetic operations. In the existing system, the FPM(Floating Point Multiplication) and FPA(Floating Point Addition) have more delay and fewer speed and fewer throughput. The demand for high speed and throughput intended to design the multiplier and adder blocks within the FPM (Floating point multiplication)and FPA(Floating Point Addition) in a format of single precision floating point and double-precision floating point operation is internally pipelined to achieve high throughput and these are supported by the IEEE 754 standard floating point representations. This is designed with the Verilog code using Xilinx ISE 14.5 software tool is employed to code and verify the ensuing waveforms of the designed code


2017 ◽  
Vol 83 (12) ◽  
pp. 1148-1155
Author(s):  
Akihisa HASEBE ◽  
Kunihito KATO ◽  
Hideki TANAHASHI ◽  
Hidekazu HIRAYU

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