A Solution to Design Semi-static Null Convention Logic Cell Libraries

The Null Convention Logic (NCL) based asynchronous circuits have eliminated the disadvantages of the synchronous circuits, including noise, glitches, clock skew, power, and electromagnetic interference. However, using NCL based asynchronous designs was not easy for students and researchers because of the lack of standard NCL cell libraries. This paper proposes a solution to design a semi-static NCL cell library used to synthesize NCL based asynchronous designs. This solution will help researchers save time and effort to approach a new method. In this work, NCL cells are designed based on the Process Design Kit 45nm technology. They are simulated at the different corners with the Ocean script and Electronic Design Automation (EDA) environment to extract the timing models and the power models. These models are used to generate a *.lib file, which is converted to a *.db file by the Design Compiler tool to form a complete library of 27 cells. In addition, we synthesize the NCL based full adders to illustrate the success of the proposed library and compare our synthesis results with the results of the other authors. The comparison results indicate that power and delay are improved significantly.

Power Consumption Improvements in AES Decryption Based on Null Convention Logic

In this paper, we propose a new asynchronous method based on a Null Convention Logic (NCL) to improve power consumption for low power integrated circuits. The reason is because the NCL based designs do not use a clock, it eliminates the problems related to the clock and its power consumption reduces significantly. To show the advantages of the selected method, we propose two design models using the synchronous circuit design method, and the NCL based asynchronous circuit design method. To test these two design models conveniently, we also propose an extra automatic test model. In this study, the AES decryption is used as an example to illustrate both methods. The two above proposed AES decryption models are simulated and synthesized at the various corners by VCS and Design Compiler tool using TSMC standard cell libraries in 65nm technology. The synthesis results of the two above mentioned models indicated that the power consumption of the NCL based asynchronous circuit model is 3 times lower than that of the synchronous circuit model, and significantly improves (from 94% to 98%) compared with the results of the other authors. The processing speed of the NCL based asynchronous circuit paradigm is able to achieve a maximum speed.

Sense Amplifier Half Buffer Based Ripple Carry Adder for IEEE 754 Standards

Addition is a specifically used indispensable computation used for most of the applications including digital systems and control systems. Adder is a primitive constituent used in the construction of digital IC; also it is an essential part of signal processing applications like DSP. The speed of an adder circuit holds a considerable influence on the total performance of digital circuits. The prime objective of this research is to design ripple carry adder using different asynchronous logics like Multithreshold null convention logic (MTNCL), Multi-threshold dual spacer dual rail delay insensitive logic (MTD3L) and proposed Sense amplifier half buffer logic (SAHB). SAHB is an asynchronous Quasi-Delay -Insensitive (QDI) method used to achieve significant functional speed of the circuit. The standard library cells (2-input AND/NAND, 2-input OR/NOR, 2-input XOR/XNOR) are designed using proposed SAHB logic to design an 8- bit Ripple Carry Adder circuit. The proposed SAHB logic design provides the solution of minimum delay with improved speed compared to the existing logic design techniques. The asynchronous logics are designed using mentor graphics tool with 130nm technology. Various performances attributes like power dissipation, delay and energy are tabulated and compared with existing logics