scholarly journals Notice of Retraction Designing of Vedic Based Modulo Multiplication in Residue Number System

2018 ◽  
Vol 7 (2) ◽  
pp. 67
Author(s):  
Shamim Akhter ◽  
Divya Bareja ◽  
Satyendra Kumar
Keyword(s):  
Comparative Analysis ◽  
Input Data ◽  
Computation Time ◽  
Number System ◽  
Residue Number System ◽  
Expert Committee ◽  
Direct Computation ◽  
Very Old ◽  
Residue Number ◽  
Mathematical Operations

<p><strong>Notice of Retraction</strong></p><p>-----------------------------------------------------------------------<br />After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IAES's Publication Principles.<br /><br />We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.<br /><br />The presenting author of this paper has the option to appeal this decision by contacting [email protected].</p><p>-----------------------------------------------------------------------</p><p>Residue Number System (RNS) is a very old number system which was proposed in 1500 AD. Parallel nature for mathematical operations in RNS results in faster computation. This paper deals with designing of modulo multiplication in RNS. Direct computation of |AB|<sub>m</sub>, requires multiplier to get A.B first and then Mod-m calculator to get the final result. We have used Vedic technique along with RNS to improve the computation time for modulo multiplication. This paper is aimed at designing and analysis of modulo multiplier for special moduli set like 3, 5 and 7. Comparative analysis in terms of area and delay is performed for input data size (N=8, 16 and 32-bit) between proposed technique and direct computation using Xilinx ISE 14.1. Design is also been compared using Synopsys Design Compiler with 32 nm Std_Cell Library. It is found that proposed technique is more efficient in terms of speed when input data size increases.</p>

scholarly journals Multiplication Technique in Residue Number System

2019 ◽  
Vol 8 (6) ◽  
pp. 1037-1041
Keyword(s):  
Computation Time ◽  
Number System ◽  
Residue Number System ◽  
Performance Comparison ◽  
Comparison Analysis ◽  
Direct Computation ◽  
Vedic Mathematics ◽  
Standard Cells ◽  
Multiplication Operation ◽  
Residue Number

This paper presents the modulo multiplication technique in residue number system (RNS) using Vedic mathematics. Residue number system supports fast mathematsical computation. In this paper, the use of the combination of RNS and Vedic mathematics has improved the computation time for modulo multiplication operation. The proposed modulo multiplier is implemented in VHDL and synthesized using Xilinx ISE 14.1.The performance comparison analysis in terms of area, power and delay is done between the proposed technique and direct computation. The performance of the multiplier circuit has been compared using the 32 nm standard cells available in Synopsys Design Compiler. The presented Vedic modulo multiplier is efficient in terms of speed for large input data sizes

scholarly journals Data Flow Oriented Hardware Design of RNS-based Polynomial Multiplication for SHE Acceleration

2018 ◽  
pp. 69-88
Author(s):  
Joël Cathébras ◽  
Alexandre Carbon ◽  
Peter Milder ◽  
Renaud Sirdey ◽  
Nicolas Ventroux
Keyword(s):  
Hardware Implementation ◽  
Computation Time ◽  
Number System ◽  
Residue Number System ◽  
Polynomial Multiplication ◽  
Basis Size ◽  
Residue Number ◽  
Speed Up ◽  
Channel Dependent ◽  
Reasonable Use

This paper presents a hardware implementation of a Residue Polynomial Multiplier (RPM), designed to accelerate the full Residue Number System (RNS) variant of the Fan-Vercauteren scheme proposed by Bajard et al. [BEHZ16]. Our design speeds up polynomial multiplication via a Negative Wrapped Convolution (NWC) which locally computes the required RNS channel dependent twiddle factors. Compared to related works, this design is more versatile regarding the addressable parameter sets for the BFV scheme. This is mainly brought by our proposed twiddle factor generator that makes the design BRAM utilization independent of the RNS basis size, with a negligible communication bandwidth usage for non-payload data. Furthermore, the generalization of a DFT hardware generator is explored in order to generate RNS friendly NTT architectures. This approach helps us to validate our RPM design over parameter sets from the work of Halevi et al. [HPS18]. For the depth-20 setting, we achieve an estimated speed up for the residue polynomial multiplications greater than 76 during ciphertexts multiplication, and greater than 16 during relinearization. It thus results in a single-threaded Mult&Relin ciphertext operation in 109.4 ms (×3.19 faster than [HPS18]) with RPM counting for less than 15% of the new computation time. Our RPM design scales up with reasonable use of hardware resources and realistic bandwidth requirements. It can also be exploited for other RNS based implementations of RLWE cryptosystems.

scholarly journals Montgomery reduction within the context of residue number system arithmetic

2017 ◽  
Vol 8 (3) ◽  
pp. 189-200 ◽  
Author(s):  
Jean-Claude Bajard ◽  
Julien Eynard ◽  
Nabil Merkiche
Keyword(s):  
Number System ◽  
Residue Number System ◽  
Residue Number ◽  
Montgomery Reduction

scholarly journals Computationally Efficient Approach to Implementation of the Chinese Remainder Theorem Algorithm in Minimally Redundant Residue Number System

2021 ◽  
Author(s):  
Mikhail Selianinau
Keyword(s):  
Chinese Remainder Theorem ◽  
Number System ◽  
Residue Number System ◽  
Computer Applications ◽  
Efficient Approach ◽  
Residue Modulo ◽  
Modern Computer ◽  
New Variant ◽  
Residue Number ◽  
Residue Code

AbstractIn this paper, we deal with the critical problem of performing non-modular operations in the Residue Number System (RNS). The Chinese Remainder Theorem (CRT) is widely used in many modern computer applications. Throughout the article, an efficient approach for implementing the CRT algorithm is described. The structure of the rank of an RNS number, a principal positional characteristic of the residue code, is investigated. It is shown that the rank of a number can be represented by a sum of an inexact rank and a two-valued correction to it. We propose a new variant of minimally redundant RNS, which provides low computational complexity for the rank calculation, and its effectiveness analyzed concerning conventional non-redundant RNS. Owing to the extension of the residue code, by adding the excess residue modulo 2, the complexity of the rank calculation goes down from $O\left (k^{2}\right )$ O k 2 to $O\left (k\right )$ O k with respect to required modular addition operations and lookup tables, where k equals the number of non-redundant RNS moduli.

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