SoC-FPGA systems for the acquisition and processing of electroencephalographic signals

<span lang="EN-US">Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip field-programmable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steady-state visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.</span>

A low power comparator utilizing MTSCStack, DTTS, and bulk-driven techniques

Comparator is one of the main blocks that play a vital task in the performance of analog to digital converters (ADC) in all modern technology devices. High-speed devices with low voltage and low power are considered essential for industrial applications. The design of a low-power comparator with high speed is required to accomplish the requirements mostly in electronic devices that are necessary for high-speed ADCs. However, a high-speed device that leads the scaling down of CMOS process technology will consume more power. Thus, power reduction techniques such as multi-threshold super cut-off stack (MTSCStack), dual-threshold transistor stacking (DTTS), a bulk-driven, and a bulk-driven differential pair were studied in this work. This study aims to find and build the combination of these techniques to produce a comparator that can operate in low power without compromising existing performance using the 0.13-µm CMOS process. A comparator with a combination of MTSCStack, DTTS, and NMOS bulk-driven differential pair shows the most promising result of 6.29 µW for static power, 17.15 µW for dynamic power, and 23.44 µW for total power.

Heuristic algorithms for dynamic scheduling of moldable tasks in multicore embedded systems

Dynamic scheduling of parallel tasks is one of the efficient techniques to achieve high performance in multicore systems. Most existing algorithms for dynamic task scheduling assume that a task runs on one of the multiple cores or a fixed number of cores. Existing researches on dynamic task scheduling methods have evaluated their methods in different experimental environments and models. In this paper, the dynamic task scheduling methods are systematically rearranged and evaluated.

FPGA based co-design of a speed fuzzy logic controller applied to an autonomous car

This paper invests in FPGA technology to control the speed of an autonomous car using fuzzy logic. For that purpose, we propose a co-design based on a novel fuzzy controller IP. It was developed using the hardware language VHDL and driven by the Zynq processor through an SDK software design written in C. The proposed IP acts according to the ambient temperature and the presence or absence of an obstacle and its distance from the car. The partitioning of the co-design tasks divides them into hardware and software parts. The simulation results of the fuzzy IP and those of the complete co-design implementation on a Xilinx Zynq board showed the effectiveness of the proposed controller to meet the target constraints and generate suitable PWM signals. The proposed hardware architecture based on 6-LUT blocks uses 11 times fewer logic resources than other previous similar designs. Also, it can be easily updated when new constraints on the system are to be considered, which makes it suitable for many related applications. Fuzzy computing was accelerated thanks to the use of digital signal processing blocks that ensure parallel processing. Indeed, a complete execution cycle takes only 7 us.

Digital brain: Model-based framework for dependable electroencephalogram sensing and actuation in internet of things system

<p>Real-time brain internet of thing (IoT) frameworks are expensive. But, creating a cheaper framework has been quickened incredibly by the superior investigation that's being done on virtual brain. The passing of an imperative individual on a mystery mission is considered delicate data and must be taken care of with as much security as conceivable. By guaranteeing this discreteness, the time taken for the message of their passing to reach the pertinent specialist is expanded to up to a few days. The time taken to provide the message is as well. These days, the advancements in equipment expanding the capacities of the virtual brain and of the wearable brain IoT sensors have made the advancement of various unused program systems conceivable for engineers to make valuable applications that combine the human brain with IoT. Different tactile pathways are too empowered for communications of the human brain with bigger measured data. The fundamental point of this extend is to transfer secret records onto the clouds safely.</p>

Image processing using a reconfigurable platform: Pre-processing block hardware architecture

<p class="CM12">Real time image processing is a challenging task in which fetching the sub image requires offset memory access apart from core processing needs. This paper aims at overcoming the offset needs for memory addressing in pre-processing blocks. Another feature of this present work is to appending the image data with customized algorithmic reequipments viz duplicating, zero padding. For KxK kernel size, the proposed hardware architecture can be programmed to fetch K pixels in one cycle, reducing the data access time. Results have been compared with software-based processing for KxK spatial filtering. performance indicates significant timing improvement using proposed pre-processing hardware block.</p>

ACCESS - IoT enabled smart lock

<div class="abstract">ACCESS is a centrally controlled extensible security system - a system for enhancing accessibility and security methods. Security is an important matter of concern and everyone wants things easy and fast with the advancement of technology. Many IoT engineers are inclined towards home automation today. An area of recent interest is the automation of lock and key systems of homes and workplaces. This paper comprises mechanisms to view visitors of households, machinery, or any appliance that may be remotely controlled through a mobile application. Owners or supervisors can keep a watch on the guests and choose whom they want to grant entry to. This is conducted by providing the guests with temporary access permission for a validity period of the owner’s choice. They can also simultaneously monitor the activities of the guests.</div>

Neural net implementation of steam properties on FPGA

Real time applications like model predictive control, monitoring and data reconciliation of power plants and industrial processes employ nonlinear mathematical models and require thermodynamic properties and their derivatives of working fluids. Applications like super heater temperature control based on energy balance and real time data reconciliation, require an efficient and a compact method for simultaneous estimation of thermodynamic properties, and their partial derivatives suitable for implementation in field-programmable gate array (FPGA). However, the complex mathematical formulations of these properties prohibit direct implementations in FPGAs. Single artificial neural network (ANN) architecture is used to replace the entire code in higher level languages, running into a few thousand lines. FPGA implementation of a compact neural network for the entire range of thermodynamic properties is presented. Large arguments in sigmoid function are factored into a product of integer and a fractional part which is represented using series approximation with five terms only and the integers are represented in look up table (LUT). This ensures optimum storage and computational burden for the above applications. The ANN is implemented in IEEE 754 floating point with synthesis in Xilinx ISE design suite using Verilog HDL. The results are presented for a typical pressure versus saturation temperature.

Enhanced MAC controller architecture for 2D processing based on FPGA with configurable resource allocation

The bulks of image processing algorithms are either two-dimensional (2D) or confined by their very nature. As a result, the 2D convolution function has a large impact on picture processing requirements. The methodology of 2D convolution and media access control (MAC) design can also be used to perform a variety of image processing tasks, and even as picture blurring, softening, and feature extraction. The main goal of this research is to develop a more efficient MAC control block-based 2D convolution architecture. This 2D algorithm can be implemented in hardware using fewer modules, multipliers, adders, and control blocks, resulting in significant hardware savings and look up table (LUT) reductions. The simulations were run in Verilog, and the Xilinx Vertex family field programmable gate array (FPGA) was used to build and test them. The recommended 2D convolution architectural solution is significantly faster and consumes significantly less hardware resources than the traditional 2D convolution implementation. The proposed architecture will result in technology that saves a substantial amount of processing time when it comes to LUTs.

FPGA implementation of Lempel-Ziv data compression

When transmitting the data in digital communication, it is well desired that the transmitting data bits should be as minimal as possible, so many techniques are used to compress the data. In this paper, a Lempel-Ziv algorithm for data compression was implemented through VHDL coding. One of the most lossless data compression algorithms commonly used is Lempel-Ziv. The work in this paper is devoted to improve the compression rate, space-saving, and utilization of the Lempel-Ziv algorithm using a systolic array approach. The developed design is validated with VHDL simulations using Xilinx ISE 14.5 and synthesized on Virtex-6 FPGA chip. The results show that our design is efficient in providing high compression rates and space-saving percentage as well as improved utilization. The Throughput is increased by 50% and the design area is decreased by more than 23% with a high compression ratio compared to comparable previous designs.