Design and Evaluation of a Reconfigurable Fault Tolerant Quantum-Dot Cellular Automata Gate

2013 ◽  
Vol 10 (2) ◽  
pp. 380-388 ◽  
Author(s):  
Arman Roohi ◽  
Samira Sayedsalehi ◽  
Hossein Khademolhosseini ◽  
Keivan Navi
Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2565
Author(s):  
Saeid Seyedi ◽  
Nima Jafari Navimipour ◽  
Akira Otsuki

Quantum-dot Cellular Automata (QCA) is an innovative paradigm bringing hopeful applications in the perceptually novel computing layout in quantum electronics. The circuits manufactured by QCA technology can provide a notable decrease in size, rapid-switching velocity, and ultra-low power utilization. The demultiplexer is a beneficial component to optimize the whole process in any logical design, and therefore is very important in QCA. Moreover, fault-tolerant circuits can improve the reliability of digital circuits by redundancy. Hence, the present investigation illustrates a novel QCA-based fault-tolerant 1:2 demultiplexer construct that employs a two-input AND gate and inverter. The functionality of the suggested layout was executed and evaluated with the utilization of the QCADesigner 2.0.3 simulator. This paper utilizes cell redundancy on the wire, inverter, and AND gates for designing a fault-tolerant demultiplexer. Four components (i.e., missing cells, dislocation cells, extra cells, and misalignment) were analyzed by the QCADesigner simulator. The simulation results demonstrated that our proposed QCA-based fault-tolerant 1:2 demultiplexer acted more efficiently than prior constructs regarding delay and fault tolerance. The proposed fault-tolerant 1:2 demultiplexer could attain high fault-tolerance when single missing cell or extra cell faults exist in the QCA layout.


2016 ◽  
Vol 15 (4) ◽  
pp. 1484-1497 ◽  
Author(s):  
Huakun Du ◽  
Hongjun Lv ◽  
Yongqiang Zhang ◽  
Fei Peng ◽  
Guangjun Xie

2018 ◽  
Vol 16 (01) ◽  
pp. 1850010 ◽  
Author(s):  
Golnaz Bahadori ◽  
Monireh Houshmand ◽  
Mariam Zomorodi-Moghadam

Quantum-dot cellular automata (QCA) is a promising emerging nanotechnology that has been attracting considerable attention due to its small feature size, ultra-low power consuming, and high clock frequency. Therefore, there have been many efforts to design computational units based on this technology. Despite these advantages of the QCA-based nanotechnologies, their implementation is susceptible to a high error rate. On the other hand, using the reversible computing leads to zero bit erasures and no energy dissipation. As the reversible computation does not lose information, the fault detection happens with a high probability. In this paper, first we propose a fault-tolerant control unit using reversible gates which improves on the previous design. The proposed design is then synthesized to the QCA technology and is simulated by the QCADesigner tool. Evaluation results indicate the performance of the proposed approach.


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