Multiprocessor systems with a global shared memory provide logically uniform data access. To hide latencies when accessing global memory each processor makes use of a private cache. Several copies of a data item may exist concurrently in the system. To guarantee consistency when updating an item a processor must invalidate copies of the item in other private caches. To exclude the effect of classical paging faults, one assumes that each processor knows its own data access sequence, but does not know the sequence of future invalidations requested by other processors. Performance of a processor with this restriction can be measured against the optimal behavior of a theoretical omniscient processor, using competitive analysis. We present a [Formula: see text]-competitive randomized online algorithm for this problem for cache size of 2, and prove a matching lower bound on the competitiveness. The algorithm is derived with the help of a new concept we call knowledge states. Finally, we show a lower bound of [Formula: see text] on the competitiveness for larger cache sizes.
Diseño e Implementación de un Multiprocessor Systems-on-Chip (MPSoC) Interconectado por una Networks-on-Chip (NoC)