2009 IEEE International Conference on 3D System Integration
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Published By IEEE

9781424445110

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Advanced 3D chip stack process for thin dies with fine pitch bumps using pre-applied inter chip fill

2009 IEEE International Conference on 3D System Integration ◽

10.1109/3dic.2009.5306555 ◽

2009 ◽

Cited By ~ 1

Author(s):

Akihiro Horibe ◽

Fumiaki Yamada

Keyword(s):

Fine Pitch

Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integration

2009 IEEE International Conference on 3D System Integration ◽

10.1109/3dic.2009.5306543 ◽

2009 ◽

Cited By ~ 22

Author(s):

Zheng Xu ◽

Adam Beece ◽

Kenneth Rose ◽

Tong Zhang ◽

Jian-Qiang Lu

Keyword(s):

Three Dimensional ◽

Electrical Characteristics

Development of wafer thinning and dicing technology for thin wafer

2009 IEEE International Conference on 3D System Integration ◽

10.1109/3dic.2009.5306548 ◽

2009 ◽

Cited By ~ 13

Author(s):

Chuichi Miyazaki ◽

Haruo Shimamoto ◽

Toshihide Uematsu ◽

Yoshiyuki Abe

Keyword(s):

Wafer Thinning

3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)

2009 IEEE International Conference on 3D System Integration ◽

10.1109/3dic.2009.5306588 ◽

2009 ◽

Cited By ~ 20

Author(s):

Yaoyao Ye ◽

Lian Duan ◽

Jiang Xu ◽

Jin Ouyang ◽

Mo Kwai Hung ◽

...

Keyword(s):

Optical Networks ◽

Multiprocessor Systems ◽

Networks On Chip ◽

Systems On Chip ◽

On Chip

System-level comparison of power delivery design for 2D and 3D ICs

2009 IEEE International Conference on 3D System Integration ◽

10.1109/3dic.2009.5306539 ◽

2009 ◽

Cited By ~ 32

Author(s):

Nauman H. Khan ◽

Syed M. Alam ◽

Soha Hassoun

Keyword(s):

Power Delivery ◽

System Level ◽

3D Ics ◽

2D And 3D

Developments of novel vertically integrated pixel sensors in the high energy physics community

2009 IEEE International Conference on 3D System Integration ◽

10.1109/3dic.2009.5306595 ◽

2009 ◽

Cited By ~ 5

Author(s):

Marcel Demarteau ◽

Yasuo Arai ◽

Hans-Gunther Moser ◽

Valerio Re

Keyword(s):

High Energy Physics ◽

High Energy ◽

Physics Community ◽

Pixel Sensors ◽

Energy Physics

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study

2009 IEEE International Conference on 3D System Integration ◽

10.1109/3dic.2009.5306587 ◽

2009 ◽

Cited By ~ 9

Author(s):

Dragomir Milojevic ◽

Trevor E. Carlson ◽

Kris Croes ◽

Riko Radojcic ◽

Diana F. Ragett ◽

...

Keyword(s):

Integrated Circuits ◽

Practical Case ◽

Tool Chain ◽

Stacked Integrated Circuits

Impacts of though-DRAM vias in 3D processor-DRAM integrated systems

2009 IEEE International Conference on 3D System Integration ◽

10.1109/3dic.2009.5306577 ◽

2009 ◽

Cited By ~ 13

Author(s):

Qi Wu ◽

Ken Rose ◽

Jian-Qiang Lu ◽

Tong Zhang

Keyword(s):

Integrated Systems

Etch, dielectrics and metal barrier-seed for low temperature through-silicon via processing

2009 IEEE International Conference on 3D System Integration ◽

10.1109/3dic.2009.5306552 ◽

2009 ◽

Cited By ~ 3

Author(s):

Keith Buchanan ◽

Stephen Burgess ◽

Kathrine Giles ◽

Matthew Muggeridge ◽

Hao Zhao

Keyword(s):

Low Temperature ◽

Through Silicon Via ◽

Metal Barrier

Development of a new self-assembled die bonder to three-dimensionally stack known good dies in batch

2009 IEEE International Conference on 3D System Integration ◽

10.1109/3dic.2009.5306524 ◽

2009 ◽

Author(s):

Takafumi Fukushima ◽

Eiji Iwata ◽

Tetsu Tanaka ◽

Mitsumasa Koyanagi

Keyword(s):

Self Assembled

2009 IEEE International Conference on 3D System IntegrationLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Advanced 3D chip stack process for thin dies with fine pitch bumps using pre-applied inter chip fill

Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integration

Development of wafer thinning and dicing technology for thin wafer

3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)

System-level comparison of power delivery design for 2D and 3D ICs

Developments of novel vertically integrated pixel sensors in the high energy physics community

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study

Impacts of though-DRAM vias in 3D processor-DRAM integrated systems

Etch, dielectrics and metal barrier-seed for low temperature through-silicon via processing

Development of a new self-assembled die bonder to three-dimensionally stack known good dies in batch

2009 IEEE International Conference on 3D System Integration
Latest Publications