Design and implementation of high performance matrix inversion based on reconfigurable processor

IEICE Electronics Express ◽

10.1587/elex.13.20160579 ◽

2016 ◽

Vol 13 (15) ◽

pp. 20160579-20160579 ◽

Author(s):

Kun Wang ◽

Li Li ◽

Feng Han ◽

Fan Feng ◽

Jun Lin

Keyword(s):

High Performance ◽

Matrix Inversion ◽

Reconfigurable Processor ◽

Design And Implementation ◽

Performance Matrix

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High performance matrix inversion based on LU factorization for multicore architectures

Proceedings of the 2011 ACM international workshop on Many task computing on grids and supercomputers - MTAGS '11 ◽

10.1145/2132876.2132885 ◽

2011 ◽

Author(s):

Jack Dongarra ◽

Mathieu Faverge ◽

Hatem Ltaief ◽

Piotr Luszczek

Keyword(s):

High Performance ◽

Matrix Inversion ◽

Lu Factorization ◽

Multicore Architectures ◽

Performance Matrix

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Design and Implementation of a High Performance Matrix Multiplier Core for Xilinx Virtex Fpgas

2003 IEEE International Workshop on Computer Architectures for Machine Perception ◽

10.1109/camp.2003.1598160 ◽

2006 ◽

Author(s):

S. Belkacemi ◽

K. Benkrid ◽

D. Crookes ◽

A. Benkrid

Keyword(s):

High Performance ◽

Design And Implementation ◽

Performance Matrix

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High performance matrix inversion of SPD matrices on graphics processors

2011 International Conference on High Performance Computing & Simulation ◽

10.1109/hpcsim.2011.5999887 ◽

2011 ◽

Author(s):

Peter Benner ◽

Pablo Ezzatti ◽

Enrique S. Quintana-Orti ◽

Alfredo Remon

Keyword(s):

High Performance ◽

Matrix Inversion ◽

Graphics Processors ◽

Performance Matrix

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High Performance Matrix Inversion on a Multi-core Platform with Several GPUs

2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing ◽

10.1109/pdp.2011.66 ◽

2011 ◽

Author(s):

Pablo Ezzatti ◽

Enrique S. Quintana-Orti ◽

Alfredo Remon

Keyword(s):

High Performance ◽

Matrix Inversion ◽

Performance Matrix

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A reconfigurable low-power high-performance matrix multiplier architecture with borrow parallel counters

Proceedings International Parallel and Distributed Processing Symposium ◽

10.1109/ipdps.2003.1213336 ◽

2004 ◽

Author(s):

Rong Lin

Keyword(s):

Low Power ◽

High Performance ◽

Performance Matrix

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The Design and Implementation of a High-Performance Portfolio Optimization Platform

2020 IEEE 23rd International Conference on Computational Science and Engineering (CSE) ◽

10.1109/cse50738.2020.00008 ◽

2020 ◽

Author(s):

Yidong Chen ◽

Zhonghua Lu ◽

Xueying Yang

Keyword(s):

Portfolio Optimization ◽

High Performance ◽

Design And Implementation

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FPGA design and implementation of Direct Matrix Inversion based on steepest descent method

2007 50th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2007.4488771 ◽

2007 ◽

Author(s):

Elie H. Sarraf ◽

Messaoud Ahmed-Ouameur ◽

Daniel Massicotte

Keyword(s):

Descent Method ◽

Matrix Inversion ◽

Steepest Descent ◽

Steepest Descent Method ◽

Fpga Design ◽

Design And Implementation

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Design and implementation of high performance array multipliers for digital circuits

2013 Students Conference on Engineering and Systems (SCES) ◽

10.1109/sces.2013.6547571 ◽

2013 ◽

Author(s):

P. Srivastava ◽

V. Vishant ◽

R. K. Singh ◽

R. K. Nagaria

Keyword(s):

High Performance ◽

Digital Circuits ◽

Design And Implementation ◽

Array Multipliers

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HIPERMA: A high performance and reconfigurable processor for SAR applications

2007 1st Asian and Pacific Conference on Synthetic Aperture Radar ◽

10.1109/apsar.2007.4418599 ◽

2007 ◽

Author(s):

Shushan Qiao ◽

Yong Hei ◽

Xinfeng Xu ◽

Bin Wu ◽

Yumei Zhou

Keyword(s):

High Performance ◽

Reconfigurable Processor

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Design and implementation of a high performance network security processor

International Journal of Electronics ◽

10.1080/00207210903289383 ◽

2010 ◽

Vol 97 (3) ◽

pp. 309-325 ◽

Author(s):

Haixin Wang ◽

Guoqiang Bai ◽

Hongyi Chen

Keyword(s):

Network Security ◽

High Performance ◽

Design And Implementation ◽

Network Security Processor ◽

Security Processor

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