High Performance Reconfigurable Elliptic Curve Cipher Processor Implementation

Elliptic Curve Encryption (ECC) has been widely used in the field of digital signatures in communication security. ECC standards and the diversification of application scenarios put forward higher requirements for the flexibility of ECC processors. Therefore, it is necessary to design a flexible and reconfigurable processor to adapt to changing standards. The cryptographic processor chip designed in this paper supports the choice of prime and binary fields, supports the maximum key length of 576 bits, uses microcode programming to achieve reconfigurable function, and significantly improves the flexibility of the dedicated cryptographic processor. At the same time, the speed of modular multiplication and modular division can be greatly improved under the condition of keeping the low level of hardware resources through a carefully designed modular unit of operation. After using FPGA for hardware implementation, it is configured into a 256-bit key length. The highest clock frequency of this design can reach 55.7MHz, occupying 12425LUTS. Compared with a similar design, the performance is also greatly improved. After MALU module optimization design, modular multiplication module division also has significant advantages in computing time consumption.

CHiPReP—A Compiler for the HiPReP High-Performance Reconfigurable Processor

This article presents CHiPReP, a C compiler for the HiPReP processor, which is a high-performance Coarse-Grained Reconfigurable Array employing Floating-Point Units. CHiPReP is an extension of the LLVM and CCF compiler frameworks. Its main contributions are (i) a Splitting Algorithm for Data Dependence Graphs, which distributes the computations of a C loop to Address-Generator Units and Processing Elements; (ii) a novel instruction clustering and scheduling heuristic; and (iii) an integrated placement, pipeline balancing and routing optimization method based on Simulated Annealing. The compiler was verified and analyzed using a cycle-accurate HiPReP simulation model.

Reconfigurable Morphological Processor for Grayscale Image Processing

Grayscale morphology is a powerful tool in image, video, and visual applications. A reconfigurable processor is proposed for grayscale image morphological processing. The architecture of the processor is a combination of a reconfigurable grayscale processing module (RGPM) and peripheral circuits. The RGPM, which consists of four grayscale computing units, conducts grayscale morphological operations and implements related algorithms of more than 100 f/s for a 1024 × 1024 image. The periphery circuits control the entire image processing and dynamic reconfiguration process. Synthesis results show that the proposed processor can provide 43.12 GOPS and achieve 8.87 GOPS/mm2 at a 220-MHz system clock. The simulation and experimental results show that the processor is suitable for high-performance embedded systems.

Iris Image Segmentation and Localization using Dynamic Reconfigurable Processor (DRP)

Recognition of the Iris is among the finest techniques in the field of bio-metrics identification, because the iris has characteristics that are unique and stay the same all through the individual’s life. Iris recognition phases are namely image acquisition, segmentation of iris, localization of iris, feature extraction of iris and matching. This paper, which is an extension of the survey paper Smaran et.al[1], concentrates purely on the procedures of image capture, segmentation as well as localization of the iris. The aim of the paper is to optimize the above mentioned processes in terms of distance of capturing the image, time taken for memory and computation requirements, using the DRP (Dynamic Re-Configurable Processor) technology, uniquely developed by Renesas Electronics (www.renesas.com).