Correction: Balasubramanian et al. Approximate Array Multipliers. Electronics 2021, 10, 630

The authors wish to correct the mistakes in Figures 3a and 4a,b of the article [...]

Analysis of Vedic, Wallace Tree and Array Multipliers

Multiplications are the most important and crucial operation in any system. They are done through the process of repetitive addition. Since speed is necessary in any factor therefore multiplication must also be done in a faster way so that they are utilized properly for a faster result. This paper gives a detailed explanation on all three multipliers and compares them accordingly. In this paper, three various multiplication methods are considered and simulated. Three structural multipliers such as Vedic, Wallace tree and array multipliers are compared and their output is shown through the FGPA. For comparison, the results of multipliers are synthesized and simulated using XILINX.ISE.14.5 tool. Later the comparison is concluded by evaluating their utilization of the device.

Approximate Array Multipliers

This article describes the design of approximate array multipliers by making vertical or horizontal cuts in an accurate array multiplier followed by different input and output assignments within the multiplier. We consider a digital image denoising application and show how different combinations of input and output assignments in an approximate array multiplier affect the quality of the denoised images. We consider the accurate array multiplier and several approximate array multipliers for synthesis. The multipliers were described in Verilog hardware description language and synthesized by Synopsys Design Compiler using a 32/28-nm complementary metal-oxide-semiconductor technology. The results show that compared to the accurate array multiplier, one of the proposed approximate array multipliers viz. PAAM01-V7 achieves a 28% reduction in critical path delay, 75.8% reduction in power, and 64.6% reduction in area while enabling the production of a denoised image that is comparable in quality to the image denoised using the accurate array multiplier. The standard design metrics such as critical path delay, total power dissipation, and area of the accurate and approximate multipliers are given, the error parameters of the approximate array multipliers are provided, and the original image, the noisy image, and the denoised images are also depicted for comparison.

Early Output Quasi-Delay-Insensitive Array Multipliers

Multiplication is a widely used arithmetic operation in microprocessing and digital signal processing applications, and multiplication is realized using a multiplier. This article presents the quasi-delay-insensitive (QDI) early output versions of recently reported indicating asynchronous array multipliers. Delay-insensitive dual-rail encoding is used for data representation and processing, and 4-phase return-to-zero (RTZ) and return-to-one (RTO) handshake protocols are used for data communication. Many QDI array multipliers were realized using a 32/28 nm complementary metal oxide semiconductor (CMOS) technology. Compared to the optimum indicating array multiplier, the proposed optimum early output array multiplier achieves a 6.2% reduction in cycle time and a 7.4% reduction in power-cycle time product (PCTP) with respect to RTZ handshaking, and a 7.6% reduction in cycle time and an 8.8% reduction in PCTP with respect to RTO handshaking without an increase in the area. The simulation results also convey that the RTO handshaking is preferable to the RTZ handshaking for the optimum implementation of QDI array multipliers.