Bounds on the Asymptotic Rate for Capacitive Crosstalk Avoidance Codes for On-Chip Buses

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e101.a.2018 ◽

2018 ◽

Vol E101.A (12) ◽

pp. 2018-2025

Author(s):

Tadashi WADAYAMA ◽

Taisuke IZUMI

Keyword(s):

Asymptotic Rate ◽

On Chip ◽

Crosstalk Avoidance

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Bounds on asymptotic rate of capacitive crosstalk avoidance codes for on-chip buses

2016 IEEE International Symposium on Information Theory (ISIT) ◽

10.1109/isit.2016.7541329 ◽

2016 ◽

Author(s):

Tadashi Wadayama ◽

Taisuke Izumi

Keyword(s):

Asymptotic Rate ◽

On Chip ◽

Crosstalk Avoidance

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Design of a novel error correction coding with crosstalk avoidance for reliable on-chip interconnection link

International Journal of Computer Applications in Technology ◽

10.1504/ijcat.2014.059097 ◽

2014 ◽

Vol 49 (1) ◽

pp. 80 ◽

Author(s):

M. Maheswari ◽

G. Seetharaman

Keyword(s):

Error Correction ◽

Error Correction Coding ◽

On Chip ◽

Crosstalk Avoidance

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A code generation algorithm of crosstalk-avoidance code with memory for low-power on-chip bus

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vdat.2008.4542440 ◽

2008 ◽

Author(s):

Kuang-Chin Cheng ◽

Jing-Yang Jou

Keyword(s):

Low Power ◽

Code Generation ◽

Generation Algorithm ◽

On Chip ◽

With Memory ◽

Crosstalk Avoidance

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Optimal low-power coding for error correction and crosstalk avoidance in on-chip data buses

Designs Codes and Cryptography ◽

10.1007/s10623-015-0084-4 ◽

2015 ◽

Vol 77 (2-3) ◽

pp. 479-491 ◽

Author(s):

Yeow Meng Chee ◽

Charles J. Colbourn ◽

Alan Chi Hung Ling ◽

Hui Zhang ◽

Xiande Zhang

Keyword(s):

Low Power ◽

Error Correction ◽

Chip Data ◽

On Chip ◽

Crosstalk Avoidance

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Selected Crosstalk Avoidance Code for Reliable Network-on-Chip

Journal of Computer Science and Technology ◽

10.1007/s11390-009-9296-2 ◽

2009 ◽

Vol 24 (6) ◽

pp. 1074-1085 ◽

Author(s):

Ying Zhang ◽

Hua-Wei Li ◽

Xiao-Wei Li

Keyword(s):

Network On Chip ◽

On Chip ◽

Crosstalk Avoidance

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Area and energy-efficient crosstalk avoidance codes for on-chip buses

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. ◽

10.1109/iccd.2004.1347891 ◽

2004 ◽

Author(s):

S.R. Sridhara ◽

A. Ahmed ◽

N.R. Shanbhag

Keyword(s):

Energy Efficient ◽

On Chip ◽

Crosstalk Avoidance

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Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link

Journal of Electronic Testing ◽

10.1007/s10836-014-5465-5 ◽

2014 ◽

Vol 30 (4) ◽

pp. 387-400 ◽

Author(s):

M. Maheswari ◽

G. Seetharaman

Keyword(s):

Error Correction ◽

Error Correction Coding ◽

On Chip ◽

Low Complex ◽

Crosstalk Avoidance

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Introduction of On-Chip Crosstalk Avoidance

On and Off-Chip Crosstalk Avoidance in VLSI Design ◽

10.1007/978-1-4419-0947-3_1 ◽

2010 ◽

pp. 3-11

Author(s):

Chunjie Duan ◽

Brock J. LaMeres ◽

Sunil P. Khatri

Keyword(s):

On Chip ◽

Crosstalk Avoidance

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A Joint-Coding Scheme With Crosstalk Avoidance in Network On Chip

TELKOMNIKA Indonesian Journal of Electrical Engineering ◽

10.11591/telkomnika.v11i1.1862 ◽

2013 ◽

Vol 11 (1) ◽

Author(s):

Lei Zhou ◽

Ning Wu ◽

Fen Ge

Keyword(s):

Network On Chip ◽

Coding Scheme ◽

On Chip ◽

Joint Coding ◽

Crosstalk Avoidance

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Code with Crosstalk Avoidance and Error Correction for Network on Chip Interconnects

2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184) ◽

10.1109/icoei48184.2020.9143002 ◽

2020 ◽

Author(s):

Kandala Anupama Satya Sai Lakshmi ◽

A.M Keerthi ◽

Kuruganti Madhu Sri ◽

M. Vinodhini

Keyword(s):

Error Correction ◽

Network On Chip ◽

On Chip ◽

Crosstalk Avoidance

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