Selected Crosstalk Avoidance Code for Reliable Network-on-Chip

Journal of Computer Science and Technology ◽

10.1007/s11390-009-9296-2 ◽

2009 ◽

Vol 24 (6) ◽

pp. 1074-1085 ◽

Author(s):

Ying Zhang ◽

Hua-Wei Li ◽

Xiao-Wei Li

Keyword(s):

Network On Chip ◽

On Chip ◽

Crosstalk Avoidance

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A Joint-Coding Scheme With Crosstalk Avoidance in Network On Chip

TELKOMNIKA Indonesian Journal of Electrical Engineering ◽

10.11591/telkomnika.v11i1.1862 ◽

2013 ◽

Vol 11 (1) ◽

Author(s):

Lei Zhou ◽

Ning Wu ◽

Fen Ge

Keyword(s):

Network On Chip ◽

Coding Scheme ◽

On Chip ◽

Joint Coding ◽

Crosstalk Avoidance

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Code with Crosstalk Avoidance and Error Correction for Network on Chip Interconnects

2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184) ◽

10.1109/icoei48184.2020.9143002 ◽

2020 ◽

Author(s):

Kandala Anupama Satya Sai Lakshmi ◽

A.M Keerthi ◽

Kuruganti Madhu Sri ◽

M. Vinodhini

Keyword(s):

Error Correction ◽

Network On Chip ◽

On Chip ◽

Crosstalk Avoidance

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Low power and reliable interconnection with combination of Crosstalk Avoidance Green Coding and capacitively charge-sharing transmitter for network-on-chip

Microelectronics Journal ◽

10.1016/j.mejo.2018.03.004 ◽

2018 ◽

Vol 75 ◽

pp. 68-74

Author(s):

Changqing Xu ◽

Yi Liu ◽

Shuai Ma ◽

YinTang Yang

Keyword(s):

Low Power ◽

Network On Chip ◽

Charge Sharing ◽

On Chip ◽

Crosstalk Avoidance

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Real Time Network on Chip (NOC) Architecture with CDMA Techniques with Audio Decoders

Oct. 17-19, 2017 Dubai (UAE) ◽

10.15242/dirpub.dir1017020 ◽

2018 ◽

Keyword(s):

Real Time ◽

Network On Chip ◽

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A congestion-aware routing algorithm for simplified mesh-of-tree architecture in network-on-chip designs

Artificial Intelligence and Industrial Application ◽

10.2495/aiia140551 ◽

2015 ◽

Author(s):

J. Fang ◽

L. Yu ◽

Z. Y. Leng

Keyword(s):

Routing Algorithm ◽

Network On Chip ◽

Tree Architecture ◽

On Chip ◽

Congestion Aware

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VLSI Design Of Low Energy Modeling For Network On Chip (NoC) Applications

i-manager’s Journal on Electronics Engineering ◽

10.26634/jele.5.1.3320 ◽

2014 ◽

Vol 5 (1) ◽

pp. 27-32

Author(s):

Jeeva Anusha ◽

◽

V. Thrimurthulu ◽

Keyword(s):

Vlsi Design ◽

Network On Chip ◽

Energy Modeling ◽

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Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

JOURNAL OF ELECTRONICS INFORMATION TECHNOLOGY ◽

10.3724/sp.j.1146.2012.00654 ◽

2014 ◽

Vol 35 (2) ◽

pp. 341-346

Author(s):

Xiao-fu Zheng ◽

Hua-xi Gu ◽

Yin-tang Yang ◽

Zhong-fan Huang

Keyword(s):

Network On Chip ◽

Low Latency ◽

Router Architecture ◽

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Example Antenna and Link Performance for Wireless Network on Chip Applications

12th European Conference on Antennas and Propagation (EuCAP 2018) ◽

10.1049/cp.2018.0956 ◽

2018 ◽

Author(s):

W. Rayess ◽

D.W. Matolak

Keyword(s):

Wireless Network ◽

Network On Chip ◽

Link Performance ◽

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An optimized path-setup method for mesh based Optical Network on Chip

2015 14th International Conference on Optical Communications and Networks (ICOCN) ◽

10.1109/icocn.2015.7203619 ◽

2015 ◽

Author(s):

Wei Tan ◽

Bowen Zhang ◽

Huaxi Gu ◽

Zheng Chen

Keyword(s):

Optical Network ◽

Network On Chip ◽

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A Novel Scheme to Map Convolutional Networks to Network-on-Chip with Computing-In-Memory Nodes

2020 International SoC Design Conference (ISOCC) ◽

10.1109/isocc50952.2020.9332940 ◽

2020 ◽

Author(s):

Jiayi Liu ◽

Kejie Huang

Keyword(s):

Network On Chip ◽

Convolutional Networks ◽

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