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Optimal low-power coding for error correction and crosstalk avoidance in on-chip data buses
Designs Codes and Cryptography
◽
10.1007/s10623-015-0084-4
◽
2015
◽
Vol 77
(2-3)
◽
pp. 479-491
◽
Cited By ~ 1
Author(s):
Yeow Meng Chee
◽
Charles J. Colbourn
◽
Alan Chi Hung Ling
◽
Hui Zhang
◽
Xiande Zhang
Keyword(s):
Low Power
◽
Error Correction
◽
Chip Data
◽
Data Buses
◽
On Chip
◽
Crosstalk Avoidance
Download Full-text
Related Documents
Cited By
References
Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
◽
10.1109/apccas.2006.342072
◽
2006
◽
Cited By ~ 2
Author(s):
Qingli Zhang
◽
Jinxiang Wang
◽
Yizheng Ye
Keyword(s):
Low Power
◽
Chip Data
◽
Data Buses
◽
On Chip
◽
Crosstalk Avoidance
Download Full-text
Dual low-power and crosstalk immune encoding scheme for on-chip data buses
Electronics Letters
◽
10.1049/el:20030934
◽
2003
◽
Vol 39
(20)
◽
pp. 1436
◽
Cited By ~ 4
Author(s):
Z. Khan
◽
A.T. Erdogan
◽
T. Arslan
Keyword(s):
Low Power
◽
Encoding Scheme
◽
Chip Data
◽
Data Buses
◽
On Chip
Download Full-text
Low power error resilient encoding for on-chip data buses
Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition
◽
10.1109/date.2002.998256
◽
2003
◽
Cited By ~ 88
Author(s):
D. Bertozzi
◽
L. Benini
◽
G. De Micheli
Keyword(s):
Low Power
◽
Error Resilient
◽
Chip Data
◽
Data Buses
◽
On Chip
Download Full-text
Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding
2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
◽
10.1109/dft.2006.22
◽
2006
◽
Cited By ~ 31
Author(s):
Partha Pande
◽
Amlan Ganguly
◽
Brett Feero
◽
Benjamin Belzer
◽
Cristian Grecu
Keyword(s):
Low Power
◽
Error Correction
◽
Forward Error Correction
◽
Error Correction Coding
◽
Networks On Chip
◽
On Chip
◽
Forward Error
◽
Crosstalk Avoidance
Download Full-text
New optimal error-correcting codes for crosstalk avoidance in on-chip data buses
Advances in Mathematics of Communications
◽
10.3934/amc.2020078
◽
2019
◽
Vol 0
(0)
◽
pp. 0-0
Author(s):
Muhammad Ajmal
◽
◽
Xiande Zhang
Keyword(s):
Error Correcting Codes
◽
Optimal Error
◽
Chip Data
◽
Data Buses
◽
On Chip
◽
Crosstalk Avoidance
Download Full-text
Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding
Journal of Electronic Testing
◽
10.1007/s10836-007-5035-1
◽
2008
◽
Vol 24
(1-3)
◽
pp. 67-81
◽
Cited By ~ 34
Author(s):
Amlan Ganguly
◽
Partha Pratim Pande
◽
Benjamin Belzer
◽
Cristian Grecu
Keyword(s):
Low Power
◽
Error Correction
◽
Error Correction Coding
◽
Networks On Chip
◽
On Chip
◽
Multiple Error
◽
Crosstalk Avoidance
Download Full-text
Design of a novel error correction coding with crosstalk avoidance for reliable on-chip interconnection link
International Journal of Computer Applications in Technology
◽
10.1504/ijcat.2014.059097
◽
2014
◽
Vol 49
(1)
◽
pp. 80
◽
Cited By ~ 7
Author(s):
M. Maheswari
◽
G. Seetharaman
Keyword(s):
Error Correction
◽
Error Correction Coding
◽
On Chip
◽
Crosstalk Avoidance
Download Full-text
A code generation algorithm of crosstalk-avoidance code with memory for low-power on-chip bus
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
◽
10.1109/vdat.2008.4542440
◽
2008
◽
Author(s):
Kuang-Chin Cheng
◽
Jing-Yang Jou
Keyword(s):
Low Power
◽
Code Generation
◽
Generation Algorithm
◽
On Chip
◽
With Memory
◽
Crosstalk Avoidance
Download Full-text
New Methodology for Combined Simulation of Delta-I Noise Interaction With Interconnect Noise for Wide, On-Chip Data-Buses Using Lossy Transmission-Line Power-Blocks
IEEE Transactions on Advanced Packaging
◽
10.1109/tadvp.2005.862647
◽
2006
◽
Vol 29
(1)
◽
pp. 11-20
◽
Cited By ~ 2
Author(s):
A. Deutsch
◽
H.H. Smith
◽
B.J. Rubin
◽
B.L. Krauter
◽
G.V. Kopcsay
Keyword(s):
Transmission Line
◽
Chip Data
◽
Lossy Transmission
◽
Data Buses
◽
Combined Simulation
◽
On Chip
◽
Lossy Transmission Line
◽
Interconnect Noise
Download Full-text
Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
◽
10.1093/ietfec/e88-a.12.3282
◽
2005
◽
Vol E88-A
(12)
◽
pp. 3282-3289
◽
Cited By ~ 8
Author(s):
S. KOMATSU
Keyword(s):
Low Power
◽
Data Transfer
◽
Fault Tolerant
◽
Chip Data
◽
Practical Applications
◽
On Chip
Download Full-text
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