IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.
Latest Publications

TOTAL DOCUMENTS

104

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0769522319

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

An automatic test pattern generation framework for combinational threshold logic networks

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. ◽

10.1109/iccd.2004.1347974 ◽

2004 ◽

Cited By ~ 6

Author(s):

P. Gupta ◽

Rui Zhang ◽

N.K. Jha

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automatic Test Pattern Generation ◽

Threshold Logic ◽

Automatic Test

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Coping with the variability of combinational logic delays

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. ◽

10.1109/iccd.2004.1347969 ◽

2004 ◽

Cited By ~ 31

Author(s):

J. Cortadella ◽

A. Kondratyev ◽

L. Lavagno ◽

C. Sotiriou

Keyword(s):

Combinational Logic

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The magic of a via-configurable regular fabric

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. ◽

10.1109/iccd.2004.1347943 ◽

2004 ◽

Author(s):

Yajun Ran ◽

M. Marek-Sadowska

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Linear programming based techniques for synthesis of network-on-chip architectures

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. ◽

10.1109/iccd.2004.1347957 ◽

2004 ◽

Cited By ~ 42

Author(s):

K. Srinivasan ◽

K.S. Chatha ◽

G. Konjevod

Keyword(s):

Linear Programming ◽

Network On Chip ◽

On Chip

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An area- and energy-efficient asynchronous booth multiplier for mobile devices

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. ◽

10.1109/iccd.2004.1347892 ◽

2004 ◽

Cited By ~ 6

Author(s):

J. Hensley ◽

A. Lastra ◽

M. Singh

Keyword(s):

Mobile Devices ◽

Energy Efficient ◽

Booth Multiplier

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Power-aware deterministic block allocation for low-power way-selective cache structure

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. ◽

10.1109/iccd.2004.1347896 ◽

2004 ◽

Cited By ~ 3

Author(s):

Jung-Wook Park ◽

Gi-Ho Park ◽

Sung-Bae Park ◽

Shin-Dug Kim

Keyword(s):

Low Power

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Layout driven optimization of datapath circuits using arithmetic reasoning

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. ◽

10.1109/iccd.2004.1347945 ◽

2004 ◽

Cited By ~ 1

Author(s):

I. Neumann ◽

D. Stoffel ◽

K. Sulimma ◽

M. Berkelaar ◽

W. Kunz

Keyword(s):

Datapath Circuits

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Exploiting quiescent states in register lifetime

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. ◽

10.1109/iccd.2004.1347948 ◽

2004 ◽

Cited By ~ 4

Author(s):

R. Sangireddy ◽

A.K. Somani

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A novel low-power scan design technique using supply gating

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. ◽

10.1109/iccd.2004.1347900 ◽

2004 ◽

Cited By ~ 2

Author(s):

S. Bhunia ◽

H. Mahmoodi ◽

S. Mukhopadhyay ◽

D. Ghosh ◽

K. Roy

Keyword(s):

Low Power ◽

Design Technique ◽

Scan Design

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Digital integrated circuit testing for art historians and test experts

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. ◽

10.1109/iccd.2004.1347889 ◽

2004 ◽

Author(s):

E. McCluskey

Keyword(s):

Integrated Circuit ◽

Circuit Testing ◽

Integrated Circuit Testing ◽

Art Historians ◽

Digital Integrated Circuit

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

An automatic test pattern generation framework for combinational threshold logic networks

Coping with the variability of combinational logic delays

The magic of a via-configurable regular fabric

Linear programming based techniques for synthesis of network-on-chip architectures

An area- and energy-efficient asynchronous booth multiplier for mobile devices

Power-aware deterministic block allocation for low-power way-selective cache structure

Layout driven optimization of datapath circuits using arithmetic reasoning

Exploiting quiescent states in register lifetime

A novel low-power scan design technique using supply gating

Digital integrated circuit testing for art historians and test experts

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.
Latest Publications