Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e93.a.2472 ◽

2010 ◽

Vol E93-A (12) ◽

pp. 2472-2480 ◽

Author(s):

Xin MAN ◽

Takashi HORIYAMA ◽

Shinji KIMURA

Keyword(s):

Power Optimization ◽

Sequential Circuits ◽

Switching Activity ◽

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A NOVEL APPROACH FOR POWER OPTIMIZATION IN SEQUENTIAL CIRCUITS USING LATCH BASED CLOCK GATING

INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING AND TECHNOLOGY ◽

10.34218/ijeet.11.4.2020.039 ◽

2020 ◽

Vol 11 (4) ◽

Author(s):

Kavya S. P. ◽

B. S. Kariyappa

Keyword(s):

Power Optimization ◽

Sequential Circuits ◽

Clock Gating ◽

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State assignment for power optimization of sequential circuits based on a probabilistic pairwise swap search algorithm

2015 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT) ◽

10.1109/isspit.2015.7394349 ◽

2015 ◽

Author(s):

Aiman H. El-Maleh

Keyword(s):

Power Optimization ◽

Search Algorithm ◽

Sequential Circuits ◽

State Assignment

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Clock-tree power optimization based on RTL clock-gating

Proceedings of the 40th conference on Design automation - DAC '03 ◽

10.1145/775832.775989 ◽

2003 ◽

Author(s):

Monica Donno ◽

Alessandro Ivaldi ◽

Luca Benini ◽

Enrico Macii

Keyword(s):

Power Optimization ◽

Clock Gating ◽

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Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks

Proceedings European Design and Test Conference. ED & TC 97 ◽

10.1109/edtc.1997.582409 ◽

2002 ◽

Author(s):

L. Benini ◽

G. De Micheli ◽

E. Macii ◽

M. Poncino ◽

R. Scarsi

Keyword(s):

Power Optimization ◽

Clock Gating ◽

Symbolic Synthesis

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Clock gating for power optimization in ASIC design cycle theory & practice

Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08 ◽

10.1145/1393921.1394003 ◽

2008 ◽

Author(s):

Jairam S ◽

Madhusudan Rao ◽

Jithendra Srinivas ◽

Parimala Vishwanath ◽

Udayakumar H ◽

...

Keyword(s):

Power Optimization ◽

Clock Gating ◽

Asic Design ◽

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Power Optimization of Communication System Using Clock Gating Technique

2015 Fifth International Conference on Advanced Computing & Communication Technologies ◽

10.1109/acct.2015.74 ◽

2015 ◽

Author(s):

Kanika Sahni ◽

Kiran Rawat ◽

Sujata Pandey ◽

Ziauddin Ahmad

Keyword(s):

Communication System ◽

Power Optimization ◽

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High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme

IEICE Transactions on Information and Systems ◽

10.1587/transinf.e93.d.2 ◽

2010 ◽

Vol E93-D (1) ◽

pp. 2-9

Author(s):

Kohei MIYASE ◽

Xiaoqing WEN ◽

Hiroshi FURUKAWA ◽

Yuta YAMATO ◽

Seiji KAJIHARA ◽

...

Keyword(s):

Switching Activity ◽

Clock Gating ◽

Scan Testing ◽

Switching Activity Reduction

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Dynamic power optimization of LFSR using clock gating

2017 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS) ◽

10.1109/iciiecs.2017.8275949 ◽

2017 ◽

Author(s):

K Madhushree ◽

Niju Rajan

Keyword(s):

Power Optimization ◽

Clock Gating ◽

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A Probabilistic Tabu Search State Assignment Algorithm for Area and Power Optimization of Sequential Circuits

Arabian Journal for Science and Engineering ◽

10.1007/s13369-020-04697-y ◽

2020 ◽

Vol 45 (8) ◽

pp. 6273-6285

Author(s):

Aiman H. El-Maleh

Keyword(s):

Tabu Search ◽

Power Optimization ◽

Sequential Circuits ◽

State Assignment ◽

Assignment Algorithm

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Power Optimization of a 32-Bit ALU Using Distributed Clock Gating Technique

Lecture Notes in Electrical Engineering - Advances in Electrical and Computer Technologies ◽

10.1007/978-981-15-5558-9_71 ◽

2020 ◽

pp. 831-841

Author(s):

Roopa R. Kulkarni ◽

S. Y. Kulkarni

Keyword(s):

Power Optimization ◽

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