Utilizing Delta IDDQ to Screen Cell Specific Defects for High Quality and Reliability Applications

High quality and reliability are paramount for automotive and other high grade commercial applications. The implementation of scan testing including stuck-at, transition, IDDQ, bridging and cell-aware patterns have all been targeted at reducing the number of defective parts being shipped. These techniques are not always sufficient to achieve sub defective parts per million (DPPM) quality levels. This paper presents a recurring failure mechanism that was encountered on an automotive device and the subsequent efforts to expand upon existing testing methodologies to effectively screen the defective devices using a delta IDDQ method with specific logic inputs and outputs. In effect, this new testing becomes a cell-aware delta IDDQ targeting one specific input condition that was implemented in production with limited test time overhead.

Enhanced Scan Segmentation for Low Power DFT

Excessive test power dissipation during scan testing of an SOC may cause reliability and yield concerns for the circuit under test (CUT). We propose an enhanced scan segmentation method using logic cluster controllability (LoCCo) technique for scan chain stitching to reduce test power efficiently. After LoCCo based scan stitching, since the trailing edge of scan chains contain very less switching transitions, we optimize the number of segments needed. This enables segmentation hardware reduction and still achieve lower power scan test compared to conventional method. Test cases prepared from ITC’99 standard circuits and industrial designs in 40nm CMOS and 28FDSOI technology were used for comparison. LoCCo based scan segmentation gave a shift power reduction of up-to 21.7% over conventional scan segmentation. Up-to 8.6%, shift power gain was observed even with 25% reduced segmentation when enhanced scan segmentation technique is used