scholarly journals High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme

2010 ◽  
Vol E93-D (1) ◽  
pp. 2-9
Author(s):  
Kohei MIYASE ◽  
Xiaoqing WEN ◽  
Hiroshi FURUKAWA ◽  
Yuta YAMATO ◽  
Seiji KAJIHARA ◽  
...  
Keyword(s):  
Switching Activity ◽  
Clock Gating ◽  
Scan Testing ◽  
Switching Activity Reduction

scholarly journals A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing

2011 ◽  
Vol E94-D (4) ◽  
pp. 833-840
Author(s):  
Yuta YAMATO ◽  
Xiaoqing WEN ◽  
Kohei MIYASE ◽  
Hiroshi FURUKAWA ◽  
Seiji KAJIHARA
Keyword(s):  
Switching Activity ◽  
Scan Testing

scholarly journals A New Method for Low Power Design of Two-Level Logic Circuits

VLSI Design ◽  
1999 ◽  
Vol 9 (2) ◽  
pp. 147-157
Author(s):  
G. Theodoridis ◽  
S. Theoharis ◽  
D. Soudris ◽  
C. Goutis
Keyword(s):  
Low Power Design ◽  
Logic Circuits ◽  
New Method ◽  
Covering Problem ◽  
Switching Activity ◽  
Network Nodes ◽  
Input Signals ◽  
Input Variables ◽  
Comparison Of The Results ◽  
Switching Activity Reduction

A new method for implementing two-level logic circuits, which exhibit minimal power dissipation, is introduced. Switching activity reduction of the logic network nodes is achieved by adding extra input signals to specific gates. Employing the statistic properties of the primary inputs, a new concept for grouping the input variables with similar features is introduced. Appropriate input variables are chosen for reducing the switching activity of a logic circuit. For that purpose, an efficient synthesis algorithm, which generates the set of all groups of the variables and solves the minimum covering problem for each group is developed. The comparison of the results, produced by the proposed method, and those from ESPRESSO shows that a substantial power reduction can be achieved.

scholarly journals Clock Gating Flip-Flop using Embedded XoR Circuitry

2021 ◽  
Author(s):  
Peiyi Zhao ◽  
William Cortes ◽  
Congyi Zhu ◽  
Tom Springer
Keyword(s):  
Power Consumption ◽  
Switching Activity ◽  
Clock Gating ◽  
Flip Flop ◽  
Dynamic Power ◽  
Data Switching

Flip flops/Pulsed latches are one of the main contributors of dynamic power consumption. In this paper, a novel flip-flop (FF) using clock gating circuitry with embedded XOR, GEMFF, is proposed. Using post layout simulation with 45nm technology, GEMFF outperforms prior stateof-the-art flip-flop by 25.1% at 10% data switching activity in terms of power consumption.

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