Data-Flow Programming Paradigm for High Level Synthesis Improvement

1993 ◽

Vol 39 (2-5) ◽

pp. 89-92 ◽

Cited By ~ 2

Author(s):

Anna Antola ◽

Fausto Distante ◽

Andrea Marchese

Keyword(s):

Data Flow ◽

High Level Synthesis ◽

Node Scheduling ◽

Data Flow Graphs ◽

High Level ◽

Flow Graphs

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Automatic distributed asynchronous control circuit generation from data flow graph for asynchronous high-level synthesis

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) ◽

10.1109/iscas.2000.856255 ◽

2002 ◽

Author(s):

Euiseok Kim ◽

Jeong-Gun Lee ◽

Dong-Ik Lee

Keyword(s):

Data Flow ◽

Control Circuit ◽

High Level Synthesis ◽

Data Flow Graph ◽

Flow Graph ◽

Asynchronous Control ◽

High Level

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Combined control flow dominated and data flow dominated high-level synthesis

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545641 ◽

2005 ◽

Cited By ~ 2

Author(s):

E. Berrebi ◽

P. Kission ◽

S. Vernalde ◽

S. De Troch ◽

J.C. Berluison ◽

...

Keyword(s):

Data Flow ◽

Control Flow ◽

High Level Synthesis ◽

Combined Control ◽

High Level

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A high-level synthesis system for digital signal processing based on enumerating data-flow graphs

Proceedings of 1998 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.1998.669463 ◽

2002 ◽

Author(s):

N. Togawa ◽

T. Hisaki ◽

M. Yanagisawa ◽

T. Ohtsuki

Keyword(s):

Signal Processing ◽

Digital Signal Processing ◽

Data Flow ◽

Digital Signal ◽

High Level Synthesis ◽

Synthesis System ◽

Data Flow Graphs ◽

High Level ◽

Flow Graphs

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High Level Synthesis of Asynchronous Circuits from Data Flow Graphs

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - Lecture Notes in Computer Science ◽

10.1007/978-3-642-24154-3_32 ◽

2011 ◽

pp. 317-330

Author(s):

Rene van Leuken ◽

Tom van Leeuwen ◽

Huib Lincklaen Arriens

Keyword(s):

Data Flow ◽

Asynchronous Circuits ◽

High Level Synthesis ◽

Data Flow Graphs ◽

High Level ◽

Flow Graphs

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High level synthesis of multi-precision data flow graphs

VLSI Design 2001. Fourteenth International Conference on VLSI Design ◽

10.1109/icvd.2001.902693 ◽

2002 ◽

Cited By ~ 7

Author(s):

V. Agrawal ◽

A. Pande ◽

M.M. Mehendale

Keyword(s):

Data Flow ◽

High Level Synthesis ◽

Precision Data ◽

Data Flow Graphs ◽

High Level ◽

Flow Graphs

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High level synthesis of data flow graphs using integer linear programming for switching power reduction

2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies ◽

10.1109/icsccn.2011.6024597 ◽

2011 ◽

Cited By ~ 1

Author(s):

S. Anbu Yazhini ◽

D.S. Harish Ram

Keyword(s):

Linear Programming ◽

Integer Linear Programming ◽

Data Flow ◽

Power Reduction ◽

High Level Synthesis ◽

Switching Power ◽

Data Flow Graphs ◽

High Level ◽

Flow Graphs

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Low cost fault tolerance against k c -cycle and k m -unit transient for loop based control data flow graphs during physically aware high level synthesis

Microelectronics Reliability ◽

10.1016/j.microrel.2017.05.023 ◽

2017 ◽

Vol 74 ◽

pp. 88-99 ◽

Cited By ~ 6

Author(s):

Anirban Sengupta ◽

Deepak Kachave

Keyword(s):

Fault Tolerance ◽

Data Flow ◽

Low Cost ◽

High Level Synthesis ◽

Control Data ◽

C Cycle ◽

Data Flow Graphs ◽

High Level ◽

Flow Graphs

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Tme scaled high-level synthesis for pipelined data-flow structures

10.1109/atw.1994.747846 ◽

2005 ◽

Author(s):

P. Arato ◽

A. Rucinski ◽

I. Jankovitz

Keyword(s):

Data Flow ◽

High Level Synthesis ◽

Flow Structures ◽

High Level

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Exploration of k c ‐cycle transient fault‐secured datapath and loop unrolling factor for control data flow graphs during high‐level synthesis

Electronics Letters ◽

10.1049/el.2014.4393 ◽

2015 ◽

Vol 51 (7) ◽

pp. 562-564 ◽

Cited By ~ 8

Author(s):

A. Sengupta

Keyword(s):

Data Flow ◽

High Level Synthesis ◽

Control Data ◽

Transient Fault ◽

Loop Unrolling ◽

C Cycle ◽

Data Flow Graphs ◽

High Level ◽

Flow Graphs

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Data-Flow Programming Paradigm for High Level Synthesis Improvement

High level synthesis through folding of data flow graphs: Optimal intra-node scheduling

Automatic distributed asynchronous control circuit generation from data flow graph for asynchronous high-level synthesis

Combined control flow dominated and data flow dominated high-level synthesis

A high-level synthesis system for digital signal processing based on enumerating data-flow graphs

High Level Synthesis of Asynchronous Circuits from Data Flow Graphs

High level synthesis of multi-precision data flow graphs

High level synthesis of data flow graphs using integer linear programming for switching power reduction

Low cost fault tolerance against k c -cycle and k m -unit transient for loop based control data flow graphs during physically aware high level synthesis

Tme scaled high-level synthesis for pipelined data-flow structures

Exploration of k c ‐cycle transient fault‐secured datapath and loop unrolling factor for control data flow graphs during high‐level synthesis

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