A ROBUST INTEGRATED COMPUTER-AIDED DESIGN PACKAGE FOR URBAN DRAINAGE NETWORKS

1994 ◽  
Vol 30 (1) ◽  
pp. 117-120 ◽  
Author(s):  
K. W. Chau ◽  
S. L. Ng
Keyword(s):  
Computer Aided Design ◽  
Water Drainage ◽  
Flow Prediction ◽  
Drainage Networks ◽  
Computer Aided ◽  
Drainage Design ◽  
Drainage Pipe ◽  
Longitudinal Profiles ◽  
Aided Design ◽  
Pascal Language

This paper presents the development and verification of a computer aided design and drafting package for medium sized municipal storm water drainage systems (DRAINAGE). The numerical model, which is designed for use on microcomputers, is written in PASCAL Language and is compiled by PC software TURBO PASCAL version 6.0. The computer package for flow prediction and drainage design applies the Colebrook White Equation and the Rational Method to route pipe flows through tree-type drainage networks, automatically adjusting drainage pipe diameters to fulfil flow requirements and backwater effects. The progrmn outputs are written as DXF files which can be read and displayed readily as drawings of drainage layout plml ,md longitudinal profiles in an AutoCAD environment. DRAINAGE replaces the timeconsuming conventional method for designing stormwater drainage networks. Although the prognun is tailored for application and use in Hong Kong, it can be easily adapted to other situations.

The Design Of Digital Test Simulator

1992 ◽  
pp. 71-81
Author(s):  
Mohamed Othman ◽  
Bambang Sunaryo Suparjo
Keyword(s):  
Computer Aided Design ◽  
Logic Circuit ◽  
Testability Analysis ◽  
Computer Aided ◽  
Digital Test ◽  
Analysis System ◽  
Aided Design ◽  
Controllability And Observability ◽  
Combinational Logic Circuit ◽  
Pascal Language

Digital Test Simulator is a Computer Aided Design (CAD) tools written in Turbo Pascal language ver. 5.0. It is a gate level simulator to measures the testability values of a combinational logic circuit. It was developed based on the testability analysis system called Computer-Aided MEsurefor LOgic Testability (CAMELOT). The measurement of the testability, controllability and observability for every nodes are based on the topologyical description of the circuit. The final results produced by simulator can be expressed in the form of table and histogram. Comparison of the various nodal testability values allows the areas of poor testability to be readily identified and the inprovement can be done to the circuits to make it more testable. Key Words: Logic circuit; Computer-Aided Design; CAMELOT approach; Digital Test Simulator

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