scholarly journals Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation

2011 ◽  
Vol 4 ◽  
pp. 232-244
Author(s):  
Keisuke Inoue ◽  
Mineo Kaneko
Keyword(s):  
High Level Synthesis ◽  
Delay Compensation ◽  
Minimum Delay ◽  
High Level

Optimal Design of a VLSI Processor with Spatially and Temporally Parallel Structure

1996 ◽  
Vol 8 (6) ◽  
pp. 516-523
Author(s):  
Michitaka Kameyama ◽  
◽  
Masayuki Sasaki
Keyword(s):  
Delay Time ◽  
Scheduling Algorithm ◽  
High Level Synthesis ◽  
Parallel Structure ◽  
Data Flow Graph ◽  
Silicon Area ◽  
Suitable Combination ◽  
Minimum Delay ◽  
High Level ◽  
Minimum Delay Time

In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to the change of the environment very quickly. Therefore, the development of special-purpose VLSI processors with minimum delay time becomes a very important subject. A suitable combination of spatially parallel and temporally parallel processing is very important to realize the minimum delay time. In this article, we present a scheduling algorithm for high-level synthesis, where the input to the scheduler is a behavioral description viewed as a data flow graph. The scheduler minimizes the delay time under the constraint of a silicon area and I/O pins.

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

2009 ◽  
Vol E92-A (12) ◽  
pp. 3169-3179 ◽  
Author(s):  
Akira OHCHI ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI
Keyword(s):  
High Level Synthesis ◽  
High Level

Exact and Practical Modulo Scheduling for High-Level Synthesis

2019 ◽  
Vol 12 (2) ◽  
pp. 1-26 ◽  
Author(s):  
Julian Oppermann ◽  
Melanie Reuter-Oppermann ◽  
Lukas Sommer ◽  
Andreas Koch ◽  
Oliver Sinnen
Keyword(s):  
High Level Synthesis ◽  
Modulo Scheduling ◽  
High Level
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