Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology

The design of advanced miniaturized ultra-low power interfaces for sensors is extremely important for energy-constrained monitoring applications, such as wearable, ingestible and implantable devices used in the health and medical field. Capacitive sensors, together with their correspondent digital-output readout interfaces, make no exception. Here, we analyse and design a capacitance-to-digital converter, based on the recently introduced iterative delay-chain discharge architecture, showing the circuit inner operating principles and the correspondent design trade-offs. A complete design case, implemented in a commercial 180 nm CMOS process, operating at 0.9 V supply for a 0–250 pF input capacitance range, is presented. The circuit, tested by means of detailed electrical simulations, shows ultra-low energy consumption (≤1.884 nJ/conversion), excellent linearity (linearity error 15.26 ppm), good robustness against process and temperature corners (conversion gain sensitivity to process corners variation of 114.0 ppm and maximum temperature sensitivity of 81.9 ppm/∘C in the −40 ∘C, +125 ∘C interval) and medium-low resolution of 10.3 effective number of bits, while using only 0.0192 mm2 of silicon area and employing 2.93 ms for a single conversion.

On the Sizing of CMOS Operational Amplifiers by Applying Many-Objective Optimization Algorithms

In CMOS integrated circuit (IC) design, operational amplifiers are one of the most useful active devices to enhance applications in analog signal processing, signal conditioning and so on. However, due to the CMOS technology downscaling, along the very large number of design variables and their trade-offs, it results difficult to reach target specifications without the application of optimization methods. For this reason, this work shows the advantages of performing many-objective optimization and this algorithm is compared to the well-known mono- and multi-objective metaheuristics, which have demonstrated their usefulness in sizing CMOS ICs. Three CMOS operational transconductance amplifiers are the case study in this work; they were sized by applying mono-, multi- and many-objective algorithms. The well-known non-dominated sorting genetic algorithm version 3 (NSGA-III) and the many-objective metaheuristic-based on the R2 indicator (MOMBI-II) were applied to size CMOS amplifiers and their sized solutions were compared to mono- and multi-objective algorithms. The CMOS amplifiers were optimized considering five targets, associated to a figure of merit (FoM), differential gain, power consumption, common-mode rejection ratio and total silicon area. The designs were performed using UMC 180 nm CMOS technology. To show the advantage of applying many-objective optimization algorithms to size CMOS amplifiers, the amplifier with the best performance was used to design a fractional-order integrator based on OTA-C filters. A variation analysis considering the process, the voltage and temperature (PVT) and a Monte Carlo analysis were performed to verify design robustness. Finally, the OTA-based fractional-order integrator was used to design a fractional-order chaotic oscillator, showing good agreement between numerical and SPICE simulations.

A Novel CMOS reconfigurable rectifier for wearable piezoelectric energy harvesters

Wearable energy harvesters have potential application in the conversion of human-motion energy into electrical energy to power smart health-monitoring devices, the textile industry, smartwatches, and glasses. These energy harvesters require optimal rectifier circuits that maximize their charging efficiencies. In this study, we present the design of a novel complementary metal-oxide semiconductor (CMOS) reconfigurable rectifier for wearable piezoelectric energy harvesters that can increase their charging efficiencies. The designed rectifier is based on standard 0.18 µm CMOS process technology considering a geometrical pattern with a total silicon area of 54.765 µm x 86.355 µm. The proposed rectifier circuit has two transmission gates (TG) that are composed of four rectifier transistors with a charge of 45 kΩ, a minimum input voltage of 500 mV and a maximum voltage of 3.3 V. Results of numerical simulations of the rectifier performance indicate a voltage conversion efficiency of 99.4% and a power conversion efficiency up to 63.3%. The proposed rectifier can be used to increase the charging efficiency of wearable piezoelectric energy harvesters.

Design of Area Efficient, Low-Power and Reliable Transmission Gate-based 10T SRAM Cell for Biomedical Application

There is an immense necessity of several kilo bytes of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs (Static Random Access Memory) dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Bio medical application eliminating the use of peripheral circuitry during the read operation. It commences the read operation directly with the help of Transmission gates with which the data stored in the storage nodes can be read, instead of using the precharge and sense amplifier circuits which suits better for the implantable devices. This topology offers smaller area, reduced delay, low power consumption as well as improved data stabilization in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45V.

A Sub-1 V Bulk-Driven Rail to Rail Dynamic Voltage Comparator with Enhanced Transconductance

Reduced voltage head room availability for input signal swing is one of the major bottlenecks in the design of circuits operating with low supply voltages which attracts investigations leading to improvement in the input signal dynamic range of such circuits. Employing bulk-driven MOSFETs (BDMOS) at the input section of the circuit is a popular technique used for increasing the input dynamic range, but the smaller bulk transconductance of the bulk-driven MOSFET degrades the performance of the circuit in comparison with that of a conventional gate-driven counterpart. A double tail voltage comparator employing BDMOS technique offering rail-to-rail input dynamic range and capable of operating at sub-1[Formula: see text]V power supply is presented in this paper. A transconductance improvement scheme is employed for the first time in the literature for a voltage comparator to overcome the major drawbacks associated with the reduced bulk transconductance of BDMOS input transistors and double tail topology permits low voltage operation. The performance parameters of the proposed voltage comparator are comparable to that of conventional gate-driven comparators, with an additional advantage of rail-to-rail input dynamic range. Pre-layout and post-layout simulations were performed in Cadence Virtuoso suite with gpdk 90[Formula: see text]nm library at power supply as low as 0.6[Formula: see text]V. The worst case delay of the proposed circuit is 0.71[Formula: see text]ns and the worst case power consumption of the circuit is 15[Formula: see text]uW. The circuit consumes a silicon area of 33[Formula: see text]μm[Formula: see text]46[Formula: see text]μm. An analytical model of the transconductance enhancement technique and delay of the proposed comparator are also presented.

An Adaptive STDP Learning Rule for Neuromorphic Systems

The promise of neuromorphic computing to develop ultra-low-power intelligent devices lies in its ability to localize information processing and memory storage in synaptic circuits much like the synapses in the brain. Spiking neural networks modeled using high-resolution synapses and armed with local unsupervised learning rules like spike time-dependent plasticity (STDP) have shown promising results in tasks such as pattern detection and image classification. However, designing and implementing a conventional, multibit STDP circuit becomes complex both in terms of the circuitry and the required silicon area. In this work, we introduce a modified and hardware-friendly STDP learning (named adaptive STDP) implemented using just 4-bit synapses. We demonstrate the capability of this learning rule in a pattern recognition task, in which a neuron learns to recognize a specific spike pattern embedded within noisy inhomogeneous Poisson spikes. Our results demonstrate that the performance of the proposed learning rule (94% using just 4-bit synapses) is similar to the conventional STDP learning (96% using 64-bit floating-point precision). The models used in this study are ideal ones for a CMOS neuromorphic circuit with analog soma and synapse circuits and mixed-signal learning circuits. The learning circuit stores the synaptic weight in a 4-bit digital memory that is updated asynchronously. In circuit simulation with Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm CMOS process design kit (PDK), the static power consumption of a single synapse and the energy per spike (to generate a synaptic current of amplitude 15 pA and time constant 3 ms) are less than 2 pW and 200 fJ, respectively. The static power consumption of the learning circuit is less than 135 pW, and the energy to process a pair of pre- and postsynaptic spikes corresponding to a single learning step is less than 235 pJ. A single 4-bit synapse (capable of being configured as excitatory, inhibitory, or shunting inhibitory) along with its learning circuitry and digital memory occupies around 17,250 μm2 of silicon area.

An on-chip TVS design to meet system level ESD protection for RS485 transceiver

RS485 interface is widely used in the area of industrial control and remote meter reading, which are often subjected to serious electrostatic damage. A new On-Chip TVS (OCT) structure without extra process modification and a novel electrostatic discharge method for RS485 transceiver IC have been proposed. It is composed of a serie of Zener diodes and fabricated in 5V/18V/24V 0.5µm CDMOS technology. A 100ns pulse width of the Transmission Line Pulsing (TLP) test is performed for this proposed OCT. The driver circuit itself can work as an ESD device as well. The OCT trigger voltage is compatible with the signal level of RS485 standard. The OCT device protection level of human-body-model (HBM) is up to 16.34kV. RS485 transceiver integrated with OCT has also been tested in order to verify its reliability. The results indicate that it can pass the IEC61000-4-2 contact ±10kV stress and IEC 61000−4−4 Electrical Fast Transient (EFT) ±2.2kV without any hard damages and latch-up issues. The RS485 transceiver integrated with the OCT allows error-free data rate transfer up to 500 kbps. The chip occupies a silicon area of 2.4×1.17mm2.

Processing Electrocardiographic Signals using a Custom Designed Sigma-Delta Modulator

This paper introduces the experimental results obtained after processing an electrocardiographic signal by a full-custom, low-complexity, Sigma-Delta Modulator integrated circuit, designed and fabricated using the C5N CMOS technology available through MOSIS. By exploiting a large oversampling ratio, it was possible to obtain an effective number of bits equal to 11 at the proposed single-bit modulator’s output. The resulting bitstream was captured with a logic-state analyzer and processed offline. After decimation and digital filtering, the electrocardiographic signal was reconstructed and plotted in the time domain. Commonly referred quality metrics over the retrieved signal were calculated. A total signal-to-noise and distortion ratio, superior to 66[Formula: see text]dB, was achieved by analyzing the entire system. The proposed approach shows the feasibility of processing electrocardiographic signals using low-cost and straightforward CMOS technology circuits. Since the proposed converter uses a single voltage supply of 1.5[Formula: see text]V, exhibits a power consumption of 38[Formula: see text][Formula: see text]W, and uses a silicon area of 0.052[Formula: see text]mm2, it is suitable for single battery-operated systems on a chip.

A Scalable Cluster-based Hierarchical Hardware Accelerator for a Cortically Inspired Algorithm

This article describes a scalable, configurable and cluster-based hierarchical hardware accelerator through custom hardware architecture for Sparsey, a cortical learning algorithm. Sparsey is inspired by the operation of the human cortex and uses a Sparse Distributed Representation to enable unsupervised learning and inference in the same algorithm. A distributed on-chip memory organization is designed and implemented in custom hardware to improve memory bandwidth and accelerate the memory read/write operations for synaptic weight matrices. Bit-level data are processed from distributed on-chip memory and custom multiply-accumulate hardware is implemented for binary and fixed-point multiply-accumulation operations. The fixed-point arithmetic and fixed-point storage are also adapted in this implementation. At 16 nm, the custom hardware of Sparsey achieved an overall 24.39× speedup, 353.12× energy efficiency per frame, and 1.43× reduction in silicon area against a state-of-the-art GPU.

Enhancement in Retention Time of 3TDRAM Using Double Gate Finfet Technology at Nanometer Regime.

Leakage current, power and area is the key challenges for VLSI designer during implementation of low power devices. In an integrated circuit number of transistors double in small silicon area every two years. There are certain limitations of cmos technology in nanometer regime out of which leakage current, leakage power, average current and average power is an important issues. In this paper, Retention time improvement in three transistor dynamic random access memory using double gate Finfet technology is proposed. Double gate finfet technology in 3TDRAM overcomes the issues related to cmos technology and it does not required additional circuitry. Proposed 3T DRAM is investigated with cmos and finfet technology at 90nm technology using cadence tool. Analysis of 3TDRAM using cmos and double gate finfet technology is carried out by variation in supply voltage and capacitance values. In double gate finfet technology leakage parameters are minimized and retention time(Th) is more improved as compared to cmos technology is observed.