While most transient analysis techniques of interconnect networks ignore the nonlinearity of the driving gates, most CMOS driver models do not take into account the distributed loads. In this paper, we propose a new CMOS driver model which can handle distributed-lumped loads for transient analysis and power dissipation analysis. The output current of the CMOS driver is represented by a linear-quadratic-exponential piecewise model, taking into account the slope of the input signal, nonlinear effects of the driver and interconnect effects of the load. The CMOS transient leakage (short-circuit) current, thus short-circuit power dissipation, can be accurately evaluated. The model provides accuracy comparable to that of SPICE3e2 with one or two orders of magnitude less computing time.
The effects of new 2030 scenario: reduction of short-circuit power and widening of voltage dips
