Explicit evaluation of short circuit power dissipation for CMOS logic structures

While most transient analysis techniques of interconnect networks ignore the nonlinearity of the driving gates, most CMOS driver models do not take into account the distributed loads. In this paper, we propose a new CMOS driver model which can handle distributed-lumped loads for transient analysis and power dissipation analysis. The output current of the CMOS driver is represented by a linear-quadratic-exponential piecewise model, taking into account the slope of the input signal, nonlinear effects of the driver and interconnect effects of the load. The CMOS transient leakage (short-circuit) current, thus short-circuit power dissipation, can be accurately evaluated. The model provides accuracy comparable to that of SPICE3e2 with one or two orders of magnitude less computing time.

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Estimation of short-circuit power dissipation and its influence on propagation delay for static CMOS gates

1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96 ◽

10.1109/iscas.1996.542133 ◽

2002 ◽

Cited By ~ 5

Author(s):

A. Hirata ◽

H. Onodera ◽

K. Tamaru

Keyword(s):

Power Dissipation ◽

Short Circuit ◽

Propagation Delay ◽

Circuit Power

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Macromodel for short circuit power dissipation of submicron CMOS inverters and its application to design CMOS buffers

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. ◽

10.1109/iscas.2003.1206250 ◽

2003 ◽

Cited By ~ 1

Author(s):

S. Ulman

Keyword(s):

Power Dissipation ◽

Short Circuit ◽

Submicron Cmos ◽

Circuit Power

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Short-circuit power driven gate sizing technique for reducing power dissipation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.407004 ◽

1995 ◽

Vol 3 (3) ◽

pp. 450-455 ◽

Cited By ~ 10

Author(s):

Uming Ko ◽

P.T. Balsara

Keyword(s):

Power Dissipation ◽

Short Circuit ◽

Reducing Power ◽

Gate Sizing ◽

Circuit Power

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An accurate simulation technique for short-circuit power dissipation based on current component isolation

10.1109/iscas.1989.100558 ◽

2003 ◽

Cited By ~ 29

Author(s):

G.Y. Yacoub ◽

W.H. Ku

Keyword(s):

Power Dissipation ◽

Short Circuit ◽

Simulation Technique ◽

Current Component ◽

Circuit Power

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Short-circuit power dissipation formulae for CMOS gates

1993 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.1993.393977 ◽

2002 ◽

Author(s):

S. Vemuru ◽

N. Scheinberg ◽

E. Smith

Keyword(s):

Power Dissipation ◽

Short Circuit ◽

Circuit Power

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Power Optimization of Delay Constrained Circuits

VLSI Design ◽

10.1155/2001/65638 ◽

2001 ◽

Vol 12 (2) ◽

pp. 125-138

Author(s):

Anshuman Nayak ◽

Malay Haldar ◽

Prith Banerjee ◽

Chunhong Chen ◽

Majid Sarrafzadeh

Keyword(s):

Power Dissipation ◽

Short Circuit ◽

Average Power ◽

Accurate Estimate ◽

Voltage Scaling ◽

Power Reduction ◽

Total Power ◽

Gate Sizing ◽

Dynamic Power ◽

Circuit Power

We present a framework for combining Voltage Scaling (VS) and Gate Sizing (GS) techniques for power optimizations. We introduce a fast heuristic for choosing gates for sizing and voltage scaling such that the total power is minimized under delay constraints. We also use a more accurate estimate for determining the power dissipation of the circuit by taking into account the short circuit power along with the dynamic power. A better model of the short circuit power is used which takes into account the load capacitance of the gates. Our results show that the combination of VS and GS perform better than the techniques applied in isolation. An average power reduction of 73% is obtained when decisions are taken assuming dynamic power only. In contrast, average power reduction is 77% when decisons include the short circuit power dissipation.

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