Operating frequency improvement on FPGA implementation of a pipeline large-FFT processor

Author(s):  
Ting-wai Siu ◽  
Chiu-Wing Sham ◽  
Francis C. M. Lau
VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-6 ◽  
Author(s):  
Péter Szántó ◽  
Gábor Szedő ◽  
Béla Fehér

This paper presents an FPGA implementation of a high-performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoffs between complexity and performance. By maximizing the operating frequency, the complexity of the filter structure can be considerably reduced compared to previous 2D architectures.


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