ADVANCE VIRUS DETECTION USING COMBINED TECHNIQUES OF PATTERN MATCHING AND DYNAMIC INSTRUCTION SEQUENCES 

2009 ◽  
Vol 4 (5) ◽  
Author(s):  
Jianyong Dai ◽  
Ratan Guha ◽  
Joohan Lee

Author(s):  
P.MUTHU KUMARAN ◽  
R.V.ASHOK PRATHAP ◽  
D. MATHAVAN

Network security has always been an important issue and its application is ready to perform powerful pattern matching to protect against virus attacks, spam and Trojan horses. However, attacks such as spam, spyware, worms, viruses, and phishing target the application layer rather than the network layer. Therefore, traditional firewalls no longer provide enough protection. However, the solutions in the literature for firewalls are not scalable, and they do not address the difficulty of an antivirus. The goal is to provide a systematic virus detection hardware solution for network security for embedded systems. Instead of placing entire matching patterns on a chip, our solution is based on an antivirus processor that works as much of the filtering information as possible onto a chip. The infrequently accessing off-chip data to make the matching mechanism scalable to large pattern sets. In the first stage, the filtering engine can filter out more than 93.1% of data as safe, using a merged shift table. Only 6.9% or less of potentially unsafe data must be precisely checked in the second stage by the exact-matching engine from off-chip memory. To reduce the memory gap and to improve the performance, we also propose three algorithms are used: 1) a skipping algorithm; 2) a cache method; and 3) a prefetching mechanism.


2005 ◽  
Vol 33 (1) ◽  
pp. 2-17 ◽  
Author(s):  
D. Colbry ◽  
D. Cherba ◽  
J. Luchini

Abstract Commercial databases containing images of tire tread patterns are currently used by product designers, forensic specialists and product application personnel to identify whether a given tread pattern matches an existing tire. Currently, this pattern matching process is almost entirely manual, requiring visual searches of extensive libraries of tire tread patterns. Our work explores a first step toward automating this pattern matching process by building on feature analysis techniques from computer vision and image processing to develop a new method for extracting and classifying features from tire tread patterns and automatically locating candidate matches from a database of existing tread pattern images. Our method begins with a selection of tire tread images obtained from multiple sources (including manufacturers' literature, Web site images, and Tire Guides, Inc.), which are preprocessed and normalized using Two-Dimensional Fast Fourier Transforms (2D-FFT). The results of this preprocessing are feature-rich images that are further analyzed using feature extraction algorithms drawn from research in computer vision. A new, feature extraction algorithm is developed based on the geometry of the 2D-FFT images of the tire. The resulting FFT-based analysis allows independent classification of the tire images along two dimensions, specifically by separating “rib” and “lug” features of the tread pattern. Dimensionality of (0,0) indicates a smooth treaded tire with no pattern; dimensionality of (1,0) and (0,1) are purely rib and lug tires; and dimensionality of (1,1) is an all-season pattern. This analysis technique allows a candidate tire to be classified according to the features of its tread pattern, and other tires with similar features and tread pattern classifications can be automatically retrieved from the database.


2017 ◽  
Vol 5 (1) ◽  
pp. 8-15
Author(s):  
Sergii Hilgurt ◽  

The multi-pattern matching is a fundamental technique found in applications like a network intrusion detection system, anti-virus, anti-worms and other signature- based information security tools. Due to rising traffic rates, increasing number and sophistication of attacks and the collapse of Moore’s law, traditional software solutions can no longer keep up. Therefore, hardware approaches are frequently being used by developers to accelerate pattern matching. Reconfigurable FPGA-based devices, providing the flexibility of software and the near-ASIC performance, have become increasingly popular for this purpose. Hence, increasing the efficiency of reconfigurable information security tools is a scientific issue now. Many different approaches to constructing hardware matching circuits on FPGAs are known. The most widely used of them are based on discrete comparators, hash-functions and finite automata. Each approach possesses its own pros and cons. None of them still became the leading one. In this paper, a method to combine several different approaches to enforce their advantages has been developed. An analytical technique to quickly advance estimate the resource costs of each matching scheme without need to compile FPGA project has been proposed. It allows to apply optimization procedures to near-optimally split the set of pattern between different approaches in acceptable time.


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