A Study of a Normalized Error Calibration Method Based on Parallel High-Speed Data Acquisition System

2015 ◽  
Vol 738-739 ◽  
pp. 551-555
Author(s):  
Wen Xian Zeng ◽  
Yang Zhao ◽  
Zhi Qiang He
Keyword(s):  
Data Acquisition ◽  
High Speed ◽  
Dynamic Balance ◽  
Data Acquisition System ◽  
Calibration Method ◽  
Acquisition System ◽  
Normalized Error ◽  
Gain Error ◽  
High Speed Data Acquisition ◽  
High Speed Data

For Offset error and Gain error brought by multi-channel parallel alternate technology in high-speed data acquisition system, this paper proposes a progressive dynamic balance of error normalized calibration method. And in the high-speed data acquisition system of 1GSPS experimental platform consisting of 8 ADC, the program is carried out by experiments. The results show that the method is simple, practical and stable and meets the design requirements.

Design and Implementation of Data Acquisition System Based on FPGA and High-Speed AD

2014 ◽  
Vol 556-562 ◽  
pp. 1515-1519 ◽  
Author(s):  
Zhi Li ◽  
Da Hua Chen
Keyword(s):  
Data Acquisition ◽  
High Speed ◽  
Data Acquisition System ◽  
Acquisition System ◽  
Analog Channel ◽  
Data Output ◽  
High Speed Data Acquisition ◽  
System Data ◽  
High Speed Data ◽  
To Receive

High speed analog signals output by test object in the field of testing and controlling is typical. This paper designed a high-speed AD data acquisition system responding to this situation. In the design of the system, data is first conditioned by the analog channel. FPGA is then employed to receive, decelerate, reorganize and store the high-speed LVDS data output by AD. Data is displayed in computer after being collected by ARM from FGPA. Real circuit designing demonstrated that the high-speed data acquisition system of AD based on 100M bandwidth of analog channel is workable.

Sign in / Sign up

Export Citation Format

Share Document