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Integrated Buffer Planning
Mapping Intimacies
◽
10.4324/9780429456183
◽
2018
◽
Author(s):
Jerzy Kozlowski
◽
Ann Peterson
Keyword(s):
Buffer Planning
Download Full-text
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Cited By
References
Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
◽
10.1587/transfun.e96.a.2467
◽
2013
◽
Vol E96.A
(12)
◽
pp. 2467-2474
Author(s):
Katherine Shu-Min LI
◽
Yingchieh HO
◽
Liang-Bi CHEN
Keyword(s):
Buffer Planning
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An effective buffer planning algorithm for IP based fixed-outline SOC placement
Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07
◽
10.1145/1228784.1228917
◽
2007
◽
Author(s):
Ou He
◽
Sheqin Dong
◽
Jinian Bian
◽
Yuchun Ma
◽
Xianlong Hong
Keyword(s):
Buffer Planning
◽
Planning Algorithm
◽
Effective Buffer
Download Full-text
Improved timing closure by early buffer planning in floor-placement design flow
Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07
◽
10.1145/1228784.1228916
◽
2007
◽
Cited By ~ 3
Author(s):
Ali Jahanian
◽
Morteza Saheb Zamani
Keyword(s):
Design Flow
◽
Timing Closure
◽
Buffer Planning
Download Full-text
Fast buffer planning and congestion optimization in interconnect-driven floorplanning
Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC
◽
10.1145/1119772.1119854
◽
2003
◽
Cited By ~ 1
Author(s):
Keith W. C. Wong
◽
Evangeline F. Y. Young
Keyword(s):
Buffer Planning
Download Full-text
Noise-aware buffer planning for interconnect-driven floorplanning
Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.
◽
10.1109/aspdac.2003.1195052
◽
2003
◽
Author(s):
Shu-Min Li
◽
Yih-Huai Cherng
◽
Yao-Wen Chang
Keyword(s):
Buffer Planning
Download Full-text
Network flow based buffer planning
Integration
◽
10.1016/s0167-9260(01)00015-3
◽
2001
◽
Vol 30
(2)
◽
pp. 143-155
◽
Cited By ~ 2
Author(s):
Xiaoping Tang
◽
D.F. Wong
Keyword(s):
Network Flow
◽
Buffer Planning
Download Full-text
Buffer planning for 3D ICs
2009 IEEE International Symposium on Circuits and Systems
◽
10.1109/iscas.2009.5118110
◽
2009
◽
Author(s):
Sheqin Dong
◽
Hongjie Bai
◽
Xianlong Hong
◽
Satoshi Goto
Keyword(s):
3D Ics
◽
Buffer Planning
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A Fast and Stable Force-Directed Placement with Implicit Buffer Planning
2005 6th International Conference on ASIC
◽
10.1109/icasic.2005.1611438
◽
2006
◽
Author(s):
Lijuan Luo
◽
Qiang Zhou
◽
Yici Cai
◽
Xianlong Hong
◽
Yibo Wang
◽
...
Keyword(s):
Buffer Planning
Download Full-text
Buffer Planning: Historical Overview
Integrated Buffer Planning
◽
10.4324/9780429456183-6
◽
2018
◽
pp. 79-116
Author(s):
Ann Peterson
Keyword(s):
Historical Overview
◽
Buffer Planning
Download Full-text
Low power clock buffer planning methodology in F-D placement for large scale circuit design
2008 Asia and South Pacific Design Automation Conference
◽
10.1109/aspdac.2008.4483977
◽
2008
◽
Author(s):
Yanfeng Wang
◽
Qiang Zhou
◽
Yici Cai
◽
Jiang Hu
◽
Xianlong Hong
◽
...
Keyword(s):
Low Power
◽
Circuit Design
◽
Large Scale
◽
Buffer Planning
◽
Planning Methodology
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