scholarly journals A Smart Camera Processing Pipeline for Image Applications Utilizing Marching Pixels

2011 ◽  
Vol 2 (3) ◽  
pp. 137-156 ◽  
Author(s):  
Michael Schmidt ◽  
Marc Reichenbach ◽  
Andreas Loos ◽  
Dietmar Fey
2019 ◽  
Vol 12 (2) ◽  
pp. 120-127 ◽  
Author(s):  
Wael Farag

Background: In this paper, a Convolutional Neural Network (CNN) to learn safe driving behavior and smooth steering manoeuvring, is proposed as an empowerment of autonomous driving technologies. The training data is collected from a front-facing camera and the steering commands issued by an experienced driver driving in traffic as well as urban roads. Methods: This data is then used to train the proposed CNN to facilitate what it is called “Behavioral Cloning”. The proposed Behavior Cloning CNN is named as “BCNet”, and its deep seventeen-layer architecture has been selected after extensive trials. The BCNet got trained using Adam’s optimization algorithm as a variant of the Stochastic Gradient Descent (SGD) technique. Results: The paper goes through the development and training process in details and shows the image processing pipeline harnessed in the development. Conclusion: The proposed approach proved successful in cloning the driving behavior embedded in the training data set after extensive simulations.


Sensors ◽  
2021 ◽  
Vol 21 (9) ◽  
pp. 2958
Author(s):  
Antonio Carlos Cob-Parro ◽  
Cristina Losada-Gutiérrez ◽  
Marta Marrón-Romera ◽  
Alfredo Gardel-Vicente ◽  
Ignacio Bravo-Muñoz

New processing methods based on artificial intelligence (AI) and deep learning are replacing traditional computer vision algorithms. The more advanced systems can process huge amounts of data in large computing facilities. In contrast, this paper presents a smart video surveillance system executing AI algorithms in low power consumption embedded devices. The computer vision algorithm, typical for surveillance applications, aims to detect, count and track people’s movements in the area. This application requires a distributed smart camera system. The proposed AI application allows detecting people in the surveillance area using a MobileNet-SSD architecture. In addition, using a robust Kalman filter bank, the algorithm can keep track of people in the video also providing people counting information. The detection results are excellent considering the constraints imposed on the process. The selected architecture for the edge node is based on a UpSquared2 device that includes a vision processor unit (VPU) capable of accelerating the AI CNN inference. The results section provides information about the image processing time when multiple video cameras are connected to the same edge node, people detection precision and recall curves, and the energy consumption of the system. The discussion of results shows the usefulness of deploying this smart camera node throughout a distributed surveillance system.


Author(s):  
Paula Ramos-Giraldo ◽  
S. Chris Reberg-Horton ◽  
Steven Mirsky ◽  
Edgar Lobaton ◽  
Anna M. Locke ◽  
...  

2010 ◽  
Vol 17 (4) ◽  
pp. 550-559 ◽  
Author(s):  
C. Hintermüller ◽  
F. Marone ◽  
A. Isenegger ◽  
M. Stampanoni

GigaScience ◽  
2017 ◽  
Vol 6 (2) ◽  
Author(s):  
Mohamed Mysara ◽  
Mercy Njima ◽  
Natalie Leys ◽  
Jeroen Raes ◽  
Pieter Monsieurs

2011 ◽  
Vol 403-408 ◽  
pp. 516-521 ◽  
Author(s):  
Sanjay Singh ◽  
Srinivasa Murali Dunga ◽  
AS Mandal ◽  
Chandra Shekhar ◽  
Santanu Chaudhury

In any remote surveillance scenario, smart cameras have to take intelligent decisions to generate summary frames to minimize communication and processing overhead. Video summary generation, in the context of smart camera, is the process of merging the information from multiple frames. A summary generation scheme based on clustering based change detection algorithm has been implemented in our smart camera system for generating frames to deliver requisite information. In this paper we propose an embedded platform based framework for implementing summary generation scheme using HW-SW Co-Design based methodology. The complete system is implemented on Xilinx XUP Virtex-II Pro FPGA board. The overall algorithm is running on PowerPC405 and some of the blocks which are computationally intensive and more frequently called are implemented in hardware using VHDL. The system is designed using Xilinx Embedded Design Kit (EDK).


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