Study of Dopant Diffusion and Defect Evolution for Advanced Ultra Shallow Junctions based on Atomistic Modeling

2007 ◽  
Author(s):  
T. Noda ◽  
W. Vandervorst ◽  
S. Felch ◽  
V. Parihar ◽  
C. Vrancken ◽  
...  
2004 ◽  
Vol 810 ◽  
Author(s):  
B. Colombeau ◽  
A.J. Smith ◽  
N.E.B. Cowern ◽  
B.J. Pawlak ◽  
F. Cristiano ◽  
...  

ABSTRACTThe formation of ultra-shallow junctions (USJs) for future integrated circuit technologies requires preamorphization and high dose boron doping to achieve high activation levels and abrupt profiles. To achieve the challenging targets set out in the semiconductor roadmap, it is crucial to reach a much better understanding of the basic physical processes taking place during USJ processing. In this paper we review current understanding of dopant-defect interactions during thermal processing of device structures – interactions which are at the heart of the dopant diffusion and activation anomalies seen in USJs. First, we recall the formation and thermal evolution of End of Range (EOR) defects upon annealing of preamorphized implants (PAI). It is shown that various types of extended defect can be formed: clusters, {113} defects and dislocation loops. During annealing, these defects exchange Si interstitial atoms and evolve following an Ostwald ripening mechanism. We review progress in developing models based on these concepts, which can accurately predict EOR defect evolution and interstitial transport between the defect layer and the surface. Based on this physically based defect modelling approach, combined with fully coupled multi-stream modelling of dopant diffusion, one can perform highly predictive simulations of boron diffusion and de/re-activation in Ge-PAI boron USJs. Agreement between simulations and experimental data is found over a wide range of experimental conditions, clearly indicating that the driving mechanism that degrades boron junction depth and activation is the dissolution of the interstitial defect band. Finally, we briefly outline some promising methods, such as co-implants and/or vacancy engineering, for further down-scaling of source-drain resistance and junction depth.


2008 ◽  
Vol 1070 ◽  
Author(s):  
Pankaj Kalra ◽  
Prashant Majhi ◽  
Hsing-Huang Tseng ◽  
Raj Jammy ◽  
Tsu-Jae King Liu

ABSTRACTThe use of millisecond annealing to meet ultra-shallow junction requirements for sub-45nm CMOS technologies is imperative. In this study, the effect of flash anneal parameters is presented. Reduced dopant diffusion and lower sheet resistance Rs is achieved for intermediate temperature Tint = 700°C (vs. 800°C). Significantly lower Rs is achieved with peak temperature Tpeak = 1300°C (vs. 1250°C). Multiple shots provide for lower Rs, albeit at the expense of increased dopant diffusion. Based on a simple quantitative model, an optimal flash anneal can achieve 82% dopant activation efficiency.


2011 ◽  
Author(s):  
G. D. Papasouliotis ◽  
L. Godet ◽  
V. Singh ◽  
R. Miura ◽  
H. Ito ◽  
...  

Author(s):  
R. Lindsay ◽  
K. Henson ◽  
W. Vandervorst ◽  
K. Maex ◽  
B. J. Pawlak ◽  
...  

2013 ◽  
Vol 2 (5) ◽  
pp. P195-P204 ◽  
Author(s):  
Masahiro Yoshimoto ◽  
Masashi Okutani ◽  
Gota Murai ◽  
Shuji Tagawa ◽  
Hiroki Saikusa ◽  
...  

Author(s):  
Mark Law ◽  
Renata Camillo-Castillo ◽  
Lance Robertson ◽  
Kevin Jones

Sign in / Sign up

Export Citation Format

Share Document