Optimization of Flash Annealing Parameters to Achieve Ultra-Shallow Junctions for sub-45nm CMOS

2008 ◽  
Vol 1070 ◽  
Author(s):  
Pankaj Kalra ◽  
Prashant Majhi ◽  
Hsing-Huang Tseng ◽  
Raj Jammy ◽  
Tsu-Jae King Liu

ABSTRACTThe use of millisecond annealing to meet ultra-shallow junction requirements for sub-45nm CMOS technologies is imperative. In this study, the effect of flash anneal parameters is presented. Reduced dopant diffusion and lower sheet resistance Rs is achieved for intermediate temperature Tint = 700°C (vs. 800°C). Significantly lower Rs is achieved with peak temperature Tpeak = 1300°C (vs. 1250°C). Multiple shots provide for lower Rs, albeit at the expense of increased dopant diffusion. Based on a simple quantitative model, an optimal flash anneal can achieve 82% dopant activation efficiency.

1997 ◽  
Vol 470 ◽  
Author(s):  
Daniel F. Downey ◽  
Sonu L. Daryanani ◽  
Marylou Meloni ◽  
Kristen M. Brown ◽  
Susan B. Felch ◽  
...  

ABSTRACT2. 0 keV 11B+, 2.2 keV 49BF2+ ion implanted and 1.0 kV Plasma Doped (PLAD) wafers of a dose of 1E15/cm2 were annealed at various times and temperatures in a variety of ambiente: 600 to 50,000 ppm O2 in N2; 5% NH3 in N2; N2O; N2 or Ar, in order to investigate the effects of the annealing ambient on the formation of ultra-shallow junctions. RGA data was collected during some (if the anneals to assist in identifying the complex surface chemistry responsible for boron out-diffusion. Subsequent to the anneals, ellipsometric, XPS, four-point probe sheet resistance and SJJVIS measurements were performed to further elucidate the effects of the different ambients on the r etained boron dose, the sheet resistance value, the RTP grown oxide layer and the junction depth. In the cases where oxygen was present, e.g. N2O and O2 in N2, an oxidation enhanced diffusion of the boron was observed. This was most dramatic for the N2O anneals, which at 1050°C 10s diffused the boron an additional 283 to 427 Å, depending on the particular doping condition and species. For the case of BF2 implants and PLAD, anneals in 5% NH3 in N2 reduced the junction depth by a nitridation reduced diffusion mechanism. RGA data indicated that the out-diffusion mechanisms for B and BF2 implanted wafers are different, with the BF2 exhibiting dopant loss mechanisms during the 950°C anneals, producing F containing compounds. B implants did not show doping loss mechanisms, ais observed by the RGA, until the 1050°C anneals and these signals did not contain F containing compounds. Equivalent effective energy boron implants of 8.9 keV BF2 vs. 2.0 keV B, however, indicated that the overall effect of the F in the BF2 implants is very beneficial in the creation of ultra-shallow junctions (compared to B implants): reducing the junction depth by 428 Å, and increasing the electrical activation (determined by SRP) by 11.7%, even though the retained dose (resulting from an increased out-diffusion of B), was decreased by 5.4%.


Author(s):  
Nik Hazura N. Hamat ◽  
Uda Hashim ◽  
Ibrahim Ahmad

Bagi merealisasikan MOSFET submikron, simpangan cetek ultra berkerintangan rendah diperlukan bagi menghalang kesan saluran pendek dan bagi meningkatkan peranti. Dalam kajian ini, pembentukan simpangan cetek ultra disimulasikan menggunakan perisian ATHENA dan Silvaco Inc. bagi memodelkan resapan dari SOD ke dalam silikon. Simpangan ultra P+N berkualiti tinggi dengan kedalaman 40 nm telah dibentuk menggunakan ciri–ciri yang baik dengan arus bocor serendah 0.5 na/cm2. Simpangan cetek kurang daripada turut diperoleh tetapi kualiti simpangan–simpangan cetek ini kurang baik disebabkan oleh arus bocor permukaan yang tinggi. Pembentukan simpangan dari resapan lapisan polisilikon di atas silikon diikuti oleh SOD di atasnya menghasilkan simpangan yang lebih cetek yang berkerintangan rendah. Kata kunci: Simpangan cetek ultra, resapan, SOD, ATHENA, MOSFET For realizing deep submicron MOSFETs, ultra shallow junctions with low sheet resistance and high doping concentrations are required to suppress short channel effects and to increase the performance. In this paper, ultra shallow junctions were simulated using ATHENA software package from Silvaco TCAD Tools to model the diffusion from spin on dopant (SOD) into silicon. High performance 40 nm P+N shallow junction fabricated by rapid thermal diffusion of B150 into silicon have been obtained. The junction showed very good characteristics with leakage currents as low as 0.5 nA/cm2. Shallow junctions less than 20 nm have also been obtained but the quality was not very good due to very high surface leakage current. Junction formation by diffusion of polysilicon layer on Si substrates then SOD layer deposition on top of it produced shallower junctions with low sheet resistance. Key words: Ultra shallow junction, MOSFET, ULSI, diffusion, spin on dopant, ATHENA, ATLAS


2008 ◽  
Author(s):  
Yan Shao ◽  
John Hautala ◽  
Larry Larson ◽  
Amitabh Jain ◽  
Edmund G. Seebauer ◽  
...  

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