FPGA Realizations of Walsh Transforms for Different Transform and Word lengths into Xilinx and Altera Chips

This paper presents FPGA realizations of Walsh transforms. The realizations are targetted for the system of arbitrary waveform generation, addition/ subtraction, multiplication, and processing of several signals based on Walsh transforms which is defined in term products of Rademacher functions. Input signals are passing through the system in serial, the output either signals or coefficients are also passing out in serial. To minimize the area utilization when the systems are realized in FPGA chips, the word lengths of every processing step have been designed carefully. Based on this, FPGA realizations of those various applications into Xilinx and Altera chips have been done. In Xilinx realizations, Xilinx ISE was used to display the results and to extract some critical parameters such as speed and static power. Meanwhile, the realizations into Altera chips have been conducted using Quartus. Comparisons of speed and power among Xilinx and Altera chip realizations are presented here even though this is not an apple to apple comparison. Finally, it can be concluded that Walsh transforms can be realized not only for the applications that have been done here, but it is potential can be used for other applications.

Design of 8-point DFT based on Rademacher Functions

This paper presents a new circuit design for 8-point DFT algorithm based on product of Rademacher functions. The design has been adopted from the famous 8-point DFT decimation in time which is mainly constructs of two 4-point and four 2-point DFTs. However, the operation of the design circuit is different. It utilized the advantage of Rademacher functions simplicity. Therefore, the proposed design is constructed form the previous design 4-point DFT which is based on product of Rademacher functions [6]. Some analysis upon number types and internal connections to achieve a more efficient circuit have been conducted. As a result, instead of four, the proposed design requires only three 2-point DFT. Several output results of the design DFT have been removed since they are equal in terms of magnitude, two negative circuit are required as a compensation. Moreover, the previous 4-point DFT has been replaced to the efficient one. This circuit is special designed for non stand alone used, the circuit must be integrated inside the proposed 8-point DFT.