Optimal Identifying Codes in Oriented Paths and Circuits

Identifying codes in graphs are related to the classical notion of dominating sets [1]. Since there first introduction in 1998 [2], they have been widely studied and extended to several application, such as: detection of faulty processor in multiprocessor systems, locating danger or threats in sensor networks. Let G=(V,E) an unoriented connected graph. The minimum identifying code in graphs is the smallest subset of vertices C, such that every vertex in V have a unique set of neighbors in C. In our work, we focus on finding minimum cardinality of an identifying code in oriented paths and circuits

Algorithm-based fault recovery of adaptively refined parallel multilevel grids

On future extreme scale computers, it is expected that faults will become an increasingly serious problem as the number of individual components grows and failures become more frequent. This is driving the interest in designing algorithms with built-in fault tolerance that can continue to operate and that can replace data even if part of the computation is lost in a failure. For fault-free computations, the use of adaptive refinement techniques in combination with finite element methods is well established. Furthermore, iterative solution techniques that incorporate information about the grid structure, such as the parallel geometric multigrid method, have been shown to be an efficient approach to solving various types of partial different equations. In this article, we present an advanced parallel adaptive multigrid method that uses dynamic data structures to store a nested sequence of meshes and the iteratively evolving solution. After a fail-stop fault, the data residing on the faulty processor will be lost. However, with suitably designed data structures, the neighbouring processors contain enough information so that a consistent mesh can be reconstructed in the faulty domain with the goal of resuming the computation without having to restart from scratch. This recovery is based on a set of carefully designed distributed algorithms that build on the existing parallel adaptive refinement routines, but which must be carefully augmented and extended.

A Note on the Pessimistic Diagnosability of Augmented Cubes

A system is t/t-diagnosable if, provided the number of faulty processor is bounded by t, all faulty processors can be isolated within a set of size at most t with at most one fault-free node mistake as a faulty one. The pessimistic diagnosability of a system G, denoted by tp(G), is the maximal number of faulty processors so that the system G is t/t-diagnosable. The augmented cube AQn, proposed by Choudum and Sunitha [Networks 40 (2) (2002) 71–84], has many attractive properties such as regularity, strong connectivity and symmetry. In this paper, we determine the pessimistic diagnosability of the n-dimensional augmented cube AQn and prove that tp(AQn)=4n−8 for n≥5.

Conditional Fault-Diameter of Torus Networks

We obtain the conditional fault-diameter of the square torus interconnection network under the condition of forbidden faulty sets (i.e. assuming that each non-faulty processor has at least one non-faulty neighbor). We show that under this condition, the square torus, whose connectivity is 4, can tolerate up to 5 faulty nodes without becoming disconnected. The conditional node connectivity is, therefore, 6. We also show that the conditional fault-diameter of the square torus is equal to the fault-free diameter plus two. With this result the torus joins a group of interconnection networks (including the hypercube and the star-graph) whose conditional fault-diameter has been shown to be only two units over the fault-free diameter. Two fault-tolerant routing algorithms are discussed based on the proposed vertex disjoint paths construction.

THE CONDITIONAL NODE CONNECTIVITY OF THE k-ARY n-CUBE

This paper derives the conditional node connectivity of the k-ary n-cube interconnection network under the condition of forbidden faulty sets (i.e. assuming that each non-faulty processor has at least one non-faulty neighbor). It is shown that under this condition and for k≥4 and n≥2, the k-ary n-cube, whose connectivity is 2n, can tolerate up to 4n-3 faulty nodes without becoming disconnected. The conditional node connectivity in this case is therefore 4n-2. For k=3 and n≥2 the established conditional node connectivity is 4n-3. The result for the remaining smaller values of k and n are also obtained.

AREA EFFICIENT LAYOUT OF BALANCED HYPERCUBES

As a multicomputer structure, the balanced hypercube is a variant of the standard hypercube for multicomputers, with desirable properties of strong connectivity, regularity, and symmetry. This structure is a special type of load balanced graph designed to tolerate processor failure. In balanced hypercubes, each processor has a backup (matching) processor that shares the same set of neighboring nodes. Therefore, tasks that run on a faulty processor can be reactivated in the backup processor to provide efficient system reconfiguration. In this paper, we study the implementation of balanced hypercubes in VLSI using the Wafer Scale Integration (VLSI/WSI) technology. Emphasis is on VLSI/WSI layout and area estimates. Our results show that the balanced hypercube can be implemented at least as efficient as the standard hypercube in an area layout and more efficient in a linear layout.