IEE Proceedings G (Electronic Circuits and Systems)
Latest Publications

TOTAL DOCUMENTS

476

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By Institution Of Electrical Engineers

0143-7089

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Implementation of digital filters via VLSI array processors

IEE Proceedings G (Electronic Circuits and Systems) ◽

10.1049/ip-g-1.1988.0011 ◽

1988 ◽

Vol 135 (2) ◽

pp. 78

Author(s):

B.G. Mertzios ◽

V.L. Syrmos

Keyword(s):

Digital Filters ◽

Array Processors ◽

Vlsi Array

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Discretionary channel routing

IEE Proceedings G (Electronic Circuits and Systems) ◽

10.1049/ip-g-1.1988.0007 ◽

1988 ◽

Vol 135 (2) ◽

pp. 45

Author(s):

H.W. Leong ◽

C.L. Liu

Keyword(s):

Channel Routing

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Design of N-dimensional multiplierless spherically symmetric FIR digital filters by transformation

IEE Proceedings G (Electronic Circuits and Systems) ◽

10.1049/ip-g-1.1988.0030 ◽

1988 ◽

Vol 135 (5) ◽

pp. 203

Author(s):

C. Charalambous

Keyword(s):

Digital Filters ◽

Spherically Symmetric ◽

Fir Digital Filters

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Computation of time response for linear networks: a novel approach

IEE Proceedings G (Electronic Circuits and Systems) ◽

10.1049/ip-g-1.1988.0023 ◽

1988 ◽

Vol 135 (4) ◽

pp. 155

Author(s):

J.C. Mandojana ◽

A. Ambardar

Keyword(s):

Time Response ◽

Linear Networks ◽

Novel Approach

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Calculation of the discrete hartley transform via the fermat number transform using a VLSI chip

IEE Proceedings G (Electronic Circuits and Systems) ◽

10.1049/ip-g-1.1988.0014 ◽

1988 ◽

Vol 135 (3) ◽

pp. 101 ◽

Cited By ~ 2

Author(s):

S. Boussakta ◽

A.G.J. Holt

Keyword(s):

Discrete Hartley Transform ◽

Hartley Transform ◽

Vlsi Chip ◽

Fermat Number

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Minimal state space realisation of 3-D systems

IEE Proceedings G (Electronic Circuits and Systems) ◽

10.1049/ip-g-1.1988.0009 ◽

1988 ◽

Vol 135 (2) ◽

pp. 65 ◽

Cited By ~ 2

Author(s):

P.N. Paraskevopoulos ◽

G.E. Antoniou ◽

S.J. Varoufakis

Keyword(s):

State Space ◽

Minimal State

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Design of a systolic array system for linear state equations

IEE Proceedings G (Electronic Circuits and Systems) ◽

10.1049/ip-g-1.1988.0031 ◽

1988 ◽

Vol 135 (5) ◽

pp. 211 ◽

Cited By ~ 1

Author(s):

S.-J. Jou ◽

C.-W. Jen

Keyword(s):

Systolic Array ◽

State Equations ◽

Linear State

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Parallel architecture modified Booth multiplier

IEE Proceedings G (Electronic Circuits and Systems) ◽

10.1049/ip-g-1.1988.0019 ◽

1988 ◽

Vol 135 (3) ◽

pp. 125 ◽

Cited By ~ 8

Author(s):

A.R. Cooper

Keyword(s):

Parallel Architecture ◽

Booth Multiplier

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Prediction of RFI demodulation in bipolar operational amplifiers

IEE Proceedings G (Electronic Circuits and Systems) ◽

10.1049/ip-g-1.1988.0005 ◽

1988 ◽

Vol 135 (1) ◽

pp. 29

Author(s):

M.T. Abuelma'atti

Keyword(s):

Operational Amplifiers

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Simple RC model for integrated multiterminal interconnections

IEE Proceedings G (Electronic Circuits and Systems) ◽

10.1049/ip-g-1.1988.0003 ◽

1988 ◽

Vol 135 (1) ◽

pp. 19

Author(s):

M. Glez. Harbour ◽

J.M. Drake

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IEE Proceedings G (Electronic Circuits and Systems)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Institution Of Electrical Engineers

Implementation of digital filters via VLSI array processors

Discretionary channel routing

Design of N-dimensional multiplierless spherically symmetric FIR digital filters by transformation

Computation of time response for linear networks: a novel approach

Calculation of the discrete hartley transform via the fermat number transform using a VLSI chip

Minimal state space realisation of 3-D systems

Design of a systolic array system for linear state equations

Parallel architecture modified Booth multiplier

Prediction of RFI demodulation in bipolar operational amplifiers

Simple RC model for integrated multiterminal interconnections

IEE Proceedings G (Electronic Circuits and Systems)
Latest Publications