2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
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(FIVE YEARS 31)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781665436540

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DTIS 2021 Organizing Committee

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) ◽

10.1109/dtis53253.2021.9505050 ◽

2021 ◽

On the Limitations of Concatenating Boolean Operations in Memristive-Based Logic-In-Memory Solutions

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) ◽

10.1109/dtis53253.2021.9505096 ◽

2021 ◽

Author(s):

Pietro Inglese ◽

Elena Ioana Vatajelu ◽

Giorgio Di Natale

Keyword(s):

Boolean Operations

Design and Optimization of Cantilever Based RF-MEMS Shunt Switch for 5G Applications

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) ◽

10.1109/dtis53253.2021.9505131 ◽

2021 ◽

Author(s):

Heba Saleh ◽

Rayan Bajwa ◽

Ibrahim Tekin ◽

Murat Kaya Yapici

Keyword(s):

Rf Mems ◽

Design And Optimization

Octantis: An Exploration Tool for Beyond von Neumann architectures

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) ◽

10.1109/dtis53253.2021.9505135 ◽

2021 ◽

Author(s):

Andrea Marchesin ◽

Giovanna Turvani ◽

Andrea Coluccio ◽

Fabrizio Riente ◽

Marco Vacca ◽

...

Keyword(s):

Von Neumann ◽

Exploration Tool

Toward an Implementation Modeling Methodology for Designing SCA resilient Cryptographic Circuits

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) ◽

10.1109/dtis53253.2021.9505109 ◽

2021 ◽

Author(s):

Gabriel Rocherolle ◽

Roselyne Chotin

Keyword(s):

Modeling Methodology

Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) ◽

10.1109/dtis53253.2021.9505101 ◽

2021 ◽

Author(s):

L. Ammoura ◽

M. L. Flottes ◽

P. Girard ◽

A. Virazel

Keyword(s):

Defect Analysis

Memory Encryption Support for an FPGA-based RISC-V Implementation

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) ◽

10.1109/dtis53253.2021.9505064 ◽

2021 ◽

Author(s):

Alessandro Cilardo

Keyword(s):

Memory Encryption

Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) ◽

10.1109/dtis53253.2021.9505098 ◽

2021 ◽

Author(s):

Payam Habiby ◽

Sebastian Huhn ◽

Rolf Drechsler

Keyword(s):

Boolean Satisfiability ◽

Test Scheduling ◽

Power Domain

Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) ◽

10.1109/dtis53253.2021.9505110 ◽

2021 ◽

Author(s):

Nooshin Nosrati ◽

Katayoon Basharkhah ◽

Hanieh Totonchi Asl ◽

Zahra Mahdavi ◽

Zainalabedin Navabi

A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) ◽

10.1109/dtis53253.2021.9505139 ◽

2021 ◽

Author(s):

Luca Zulberti ◽

Pietro Nannipieri ◽

Luca Fanucci

Keyword(s):

System On Chip ◽

Speed Up ◽

On Chip

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

DTIS 2021 Organizing Committee

On the Limitations of Concatenating Boolean Operations in Memristive-Based Logic-In-Memory Solutions

Design and Optimization of Cantilever Based RF-MEMS Shunt Switch for 5G Applications

Octantis: An Exploration Tool for Beyond von Neumann architectures

Toward an Implementation Modeling Methodology for Designing SCA resilient Cryptographic Circuits

Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures

Memory Encryption Support for an FPGA-based RISC-V Implementation

Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability

Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester

A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
Latest Publications