2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
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(FIVE YEARS 39)

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9781728194578

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A novel Network-on-Chip security algorithm for tolerating Byzantine faults

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft50435.2020.9250906 ◽

2020 ◽

Author(s):

Soultana Ellinidou ◽

Gaurav Sharma ◽

Olivier Markowitch ◽

Guy Gogniat ◽

Jean-Michel Dricot

Keyword(s):

Network On Chip ◽

Byzantine Faults ◽

Security Algorithm ◽

On Chip

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Validation Challenges in Recent Trends of Power Management in Microprocessors

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft50435.2020.9250842 ◽

2020 ◽

Author(s):

Nagabhushan Reddy ◽

Sankaran Menon ◽

Prashant D. Joshi

Keyword(s):

Power Management ◽

Recent Trends

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[DFT 2020 Front cover]

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft50435.2020.9250775 ◽

2020 ◽

Keyword(s):

Front Cover

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DFT 2020 Committees

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft50435.2020.9250804 ◽

2020 ◽

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A Lightweight Reconfigurable RRAM-based PUF for Highly Secure Applications

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft50435.2020.9250829 ◽

2020 ◽

Author(s):

Basma Hajri ◽

Mohammad M. Mansour ◽

Ali Chehab ◽

Hassen Aziza

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AI in space: applications examples and challenges

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft50435.2020.9250908 ◽

2020 ◽

Author(s):

Gianluca Furano ◽

Antonis Tavoularis ◽

Marco Rovatti

Keyword(s):

Space Applications

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Hardware Accelerator Design with Supervised Machine Learning for Solar Particle Event Prediction

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft50435.2020.9250856 ◽

2020 ◽

Author(s):

J. Chen ◽

T. Lange ◽

M. Andjelkovic ◽

A. Simevski ◽

M. Krstic

Keyword(s):

Machine Learning ◽

Supervised Machine Learning ◽

Hardware Accelerator ◽

Particle Event ◽

Solar Particle ◽

Solar Particle Event ◽

Event Prediction ◽

Accelerator Design

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A Pipelined Multi-Level Fault Injector for Deep Neural Networks

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft50435.2020.9250866 ◽

2020 ◽

Author(s):

Annachiara Ruospo ◽

Angelo Balaara ◽

Alberto Bosio ◽

Ernesto Sanchez

Keyword(s):

Neural Networks ◽

Deep Neural Networks ◽

Multi Level

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Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft50435.2020.9250865 ◽

2020 ◽

Author(s):

Lucas Matana Luza ◽

Daniel Soderstrom ◽

Georgios Tsiligiannis ◽

Helmut Puchner ◽

Carlo Cazzaniga ◽

...

Keyword(s):

Soft Errors ◽

Approximate Computing ◽

Computing Systems ◽

Radiation Induced ◽

The Impact

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Variation-Aware Test for Logic Interconnects using Neural Networks – A Case Study

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft50435.2020.9250922 ◽

2020 ◽

Author(s):

Alexander Sprenger ◽

Somayeh Sadeghi-Kohan ◽

Jan Dennis Reimer ◽

Sybille Hellebrand

Keyword(s):

Neural Networks

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2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A novel Network-on-Chip security algorithm for tolerating Byzantine faults

Validation Challenges in Recent Trends of Power Management in Microprocessors

[DFT 2020 Front cover]

DFT 2020 Committees

A Lightweight Reconfigurable RRAM-based PUF for Highly Secure Applications

AI in space: applications examples and challenges

Hardware Accelerator Design with Supervised Machine Learning for Solar Particle Event Prediction

A Pipelined Multi-Level Fault Injector for Deep Neural Networks

Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems

Variation-Aware Test for Logic Interconnects using Neural Networks – A Case Study

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Latest Publications