2009 10th International Symposium on Quality of Electronic Design
Latest Publications

TOTAL DOCUMENTS

156

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781424429523

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs

2009 10th International Symposium on Quality of Electronic Design ◽

10.1109/isqed.2009.4810266 ◽

2009 ◽

Cited By ~ 3

Author(s):

Hariharan Sankaran ◽

Srinivas Katkoori

Keyword(s):

Pattern Detection ◽

Worst Case ◽

Macro Cell ◽

On Chip

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Worst case timing jitter and amplitude noise in differential signaling

2009 10th International Symposium on Quality of Electronic Design ◽

10.1109/isqed.2009.4810267 ◽

2009 ◽

Cited By ~ 2

Author(s):

Wei Yao ◽

Yiyu Shi ◽

Lei He ◽

Sudhakar Pamarti ◽

Yu Hu

Keyword(s):

Timing Jitter ◽

Worst Case ◽

Amplitude Noise ◽

Differential Signaling

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Estimation and optimization of reliability of noisy digital circuits

2009 10th International Symposium on Quality of Electronic Design ◽

10.1109/isqed.2009.4810296 ◽

2009 ◽

Cited By ~ 10

Author(s):

Satish Sivaswamy ◽

Kia Bazargan ◽

Marc Riedel

Keyword(s):

Digital Circuits

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Power estimation methodology for a high-level synthesis framework

2009 10th International Symposium on Quality of Electronic Design ◽

10.1109/isqed.2009.4810352 ◽

2009 ◽

Cited By ~ 11

Author(s):

Sumit Ahuja ◽

Deepak A. Mathaikutty ◽

Gaurav Singh ◽

Joe Stetzer ◽

Sandeep K. Shukla ◽

...

Keyword(s):

Power Estimation ◽

High Level Synthesis ◽

High Level

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SRAM supply voltage scaling: A reliability perspective

2009 10th International Symposium on Quality of Electronic Design ◽

10.1109/isqed.2009.4810392 ◽

2009 ◽

Cited By ~ 15

Author(s):

Animesh Kumar ◽

Jan Rabaey ◽

Kannan Ramchandran

Keyword(s):

Supply Voltage ◽

Voltage Scaling ◽

Supply Voltage Scaling

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Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technology

2009 10th International Symposium on Quality of Electronic Design ◽

10.1109/isqed.2009.4810357 ◽

2009 ◽

Cited By ~ 10

Author(s):

Syed M. Alam ◽

Robert E. Jones ◽

Scott Pozder ◽

Ankur Jain

Keyword(s):

Three Dimensional ◽

3D Integration ◽

Integration Technology

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Functionally valid gate-level peak power estimation for processors

2009 10th International Symposium on Quality of Electronic Design ◽

10.1109/isqed.2009.4810387 ◽

2009 ◽

Cited By ~ 5

Author(s):

Sriram Sambamurthy ◽

Sankar Gurumurthy ◽

Ramtilak Vemu ◽

Jacob A. Abraham

Keyword(s):

Peak Power ◽

Power Estimation

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VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models

2009 10th International Symposium on Quality of Electronic Design ◽

10.1109/isqed.2009.4810351 ◽

2009 ◽

Cited By ~ 2

Author(s):

Shu-Hsuan Chou ◽

Che-Neng Wen ◽

Yan-Ling Liu ◽

Tien-Fu Chen

Keyword(s):

Hardware Description Language ◽

Description Language ◽

Hardware Description

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NBTI-aware statistical circuit delay assessment

2009 10th International Symposium on Quality of Electronic Design ◽

10.1109/isqed.2009.4810263 ◽

2009 ◽

Cited By ~ 8

Author(s):

Balaji Vaidyanathan ◽

Anthony S. Oates ◽

Yuan Xie ◽

Yu Wang

Keyword(s):

Circuit Delay

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A case study on logic diagnosis for System-on-Chip

2009 10th International Symposium on Quality of Electronic Design ◽

10.1109/isqed.2009.4810303 ◽

2009 ◽

Cited By ~ 4

Author(s):

Y. Benabboud ◽

A. Bosio ◽

P. Girard ◽

S. Pravossoudovitch ◽

A. Virazel ◽

...

Keyword(s):

System On Chip ◽

On Chip

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2009 10th International Symposium on Quality of Electronic DesignLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs

Worst case timing jitter and amplitude noise in differential signaling

Estimation and optimization of reliability of noisy digital circuits

Power estimation methodology for a high-level synthesis framework

SRAM supply voltage scaling: A reliability perspective

Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technology

Functionally valid gate-level peak power estimation for processors

VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models

NBTI-aware statistical circuit delay assessment

A case study on logic diagnosis for System-on-Chip

2009 10th International Symposium on Quality of Electronic Design
Latest Publications