Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0780395719

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Automated clock inference for stream function-based system level specifications

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568815 ◽

2006 ◽

Cited By ~ 2

Author(s):

J.-P. Talpin ◽

S.K. Shukla

Keyword(s):

Stream Function ◽

System Level

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Scalable defect mapping and configuration of memory-based nanofabrics

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568807 ◽

2006 ◽

Cited By ~ 3

Author(s):

Chen He ◽

M.F. Jacome ◽

G. de Veciana

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Improvement of fault injection techniques based on VHDL code modification

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568808 ◽

2006 ◽

Cited By ~ 26

Author(s):

J.C. Baraza ◽

J. Gracia ◽

D. Gil ◽

P.J. Gil

Keyword(s):

Fault Injection ◽

Injection Techniques ◽

Vhdl Code ◽

Code Modification

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Sequential equivalence checking based on k-th invariants and circuit SAT solving

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568812 ◽

2006 ◽

Cited By ~ 9

Author(s):

F. Lu ◽

K.-T. Cheng

Keyword(s):

Equivalence Checking ◽

Sat Solving ◽

Sequential Equivalence Checking

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Formal verification of high-level conformance with symbolic simulation

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568830 ◽

2006 ◽

Cited By ~ 1

Author(s):

R. Kaivola ◽

A. Naik

Keyword(s):

Formal Verification ◽

Symbolic Simulation ◽

High Level

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Simulation-based functional test generation for embedded processors

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568806 ◽

2006 ◽

Cited By ~ 1

Author(s):

C.H.-P. Wen ◽

L.-C. Wang ◽

Kwang-Ting Cheng

Keyword(s):

Test Generation ◽

Functional Test ◽

Embedded Processors ◽

Simulation Based

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Multi-level design validation in a secure embedded system

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568838 ◽

2006 ◽

Author(s):

D.D. Hwang ◽

P. Schaumont ◽

Shenglin Yang ◽

I. Verbauwhede

Keyword(s):

Embedded System ◽

Design Validation ◽

Multi Level ◽

Level Design

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A method for generation of GSTE assertion graphs

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568831 ◽

2006 ◽

Author(s):

E. Smith

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MVP: a mutation-based validation paradigm

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568809 ◽

2006 ◽

Cited By ~ 2

Author(s):

J. Campos ◽

H. Al-Asaad

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Stimulus generation for interface protocol verification using the non-deterministic extended finite state machine model

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568819 ◽

2006 ◽

Cited By ~ 4

Author(s):

Che-Hua Shih ◽

Juinn-Dar Huang ◽

Jing-Yang Jou

Keyword(s):

Finite State Machine ◽

State Machine ◽

Protocol Verification ◽

Machine Model ◽

Finite State ◽

Stimulus Generation ◽

Extended Finite State Machine ◽

Interface Protocol

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Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Automated clock inference for stream function-based system level specifications

Scalable defect mapping and configuration of memory-based nanofabrics

Improvement of fault injection techniques based on VHDL code modification

Sequential equivalence checking based on k-th invariants and circuit SAT solving

Formal verification of high-level conformance with symbolic simulation

Simulation-based functional test generation for embedded processors

Multi-level design validation in a secure embedded system

A method for generation of GSTE assertion graphs

MVP: a mutation-based validation paradigm

Stimulus generation for interface protocol verification using the non-deterministic extended finite state machine model

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.
Latest Publications