Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.
Latest Publications

TOTAL DOCUMENTS

47

(FIVE YEARS 0)

H-INDEX

5

(FIVE YEARS 0)

Published By IEEE

0780395719

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Automated clock inference for stream function-based system level specifications

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568815 ◽

2006 ◽

Author(s):

J.-P. Talpin ◽

S.K. Shukla

Keyword(s):

Stream Function ◽

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Improvement of fault injection techniques based on VHDL code modification

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568808 ◽

2006 ◽

Author(s):

J.C. Baraza ◽

J. Gracia ◽

D. Gil ◽

P.J. Gil

Keyword(s):

Fault Injection ◽

Injection Techniques ◽

Vhdl Code ◽

Code Modification

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Sequential equivalence checking based on k-th invariants and circuit SAT solving

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568812 ◽

2006 ◽

Author(s):

F. Lu ◽

K.-T. Cheng

Keyword(s):

Equivalence Checking ◽

Sat Solving ◽

Sequential Equivalence Checking

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Scalable defect mapping and configuration of memory-based nanofabrics

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568807 ◽

2006 ◽

Author(s):

Chen He ◽

M.F. Jacome ◽

G. de Veciana

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Formal verification of high-level conformance with symbolic simulation

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568830 ◽

2006 ◽

Author(s):

R. Kaivola ◽

A. Naik

Keyword(s):

Formal Verification ◽

Symbolic Simulation ◽

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Simulation-based functional test generation for embedded processors

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568806 ◽

2006 ◽

Author(s):

C.H.-P. Wen ◽

L.-C. Wang ◽

Kwang-Ting Cheng

Keyword(s):

Test Generation ◽

Functional Test ◽

Embedded Processors ◽

Simulation Based

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Stimulus generation for interface protocol verification using the non-deterministic extended finite state machine model

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568819 ◽

2006 ◽

Author(s):

Che-Hua Shih ◽

Juinn-Dar Huang ◽

Jing-Yang Jou

Keyword(s):

Finite State Machine ◽

State Machine ◽

Protocol Verification ◽

Machine Model ◽

Finite State ◽

Stimulus Generation ◽

Extended Finite State Machine ◽

Interface Protocol

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Advanced analysis techniques for cross-product coverage

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568842 ◽

2006 ◽

Author(s):

H. Azatchi ◽

L. Fournier ◽

A. Ziv ◽

K. Zohar

Keyword(s):

Cross Product ◽

Analysis Techniques ◽

Advanced Analysis

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Cosimulation of ITRON-based embedded software with systemc

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568816 ◽

2006 ◽

Author(s):

S. Chikada ◽

S. Honda ◽

H. Tomiyama ◽

H. Takada

Keyword(s):

Embedded Software

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Security evaluation against electromagnetic analysis at design time

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. ◽

10.1109/hldvt.2005.1568839 ◽

2006 ◽

Author(s):

Huiyun Li ◽

A.T. Markettos ◽

S. Moore

Keyword(s):

Security Evaluation ◽

Electromagnetic Analysis ◽

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