Research of Parallel Computing Neuro-fuzzy Networks for Unmanned Vehicles

The Doctoral Thesis illustrates the author’s research in the field of VHDL based ‘neuro-fuzzy controllers’. The Thesis examines a novel software tool for the high-level ‘neuro-fuzzy controller’ description capable of executing controller simulations, optimisation tasks, performing learning / training tasks, and exporting the controller in VHDL code. The author introduces a design strategy that is looking for developing solutions for complex controller architecture of mobile robotic vehicles (of any nature) or even for multiple industrial application. This work enables further investigative research into autonomous robotics, particularly into the physical implementation of an autonomous aerial unmanned vehicle from an inexpensive RC plane.

Resistance of the Montgomery Ladder Against Simple SCA: Theory and Practice

The Montgomery kP algorithm i.e. the Montgomery ladder is reported in literature as resistant against simple SCA due to the fact that the processing of each key bit value of the scalar k is done using the same sequence of operations. We implemented the Montgomery kP algorithm using Lopez-Dahab projective coordinates for the NIST elliptic curve B-233. We instantiated the same VHDL code for a wide range of clock frequencies for the same target FPGA and using the same compiler options. We measured electromagnetic traces of the kP executions using the same input data, i.e. scalar k and elliptic curve point P, and measurement setup. Additionally, we synthesized the same VHDL code for two IHP CMOS technologies, for a broad spectrum of frequencies. We simulated the power consumption of each synthesized design during an execution of the kP operation, always using the same scalar k and elliptic curve point P as inputs. Our experiments clearly show that the success of simple electromagnetic analysis attacks against FPGA implementations as well as the one of simple power analysis attacks against synthesized ASIC designs depends on the target frequency for which the design was implemented and at which it is executed significantly. In our experiments the scalar k was successfully revealed via simple visual inspection of the electromagnetic traces of the FPGA for frequencies from 40 to 100 MHz when standard compile options were used as well as from 50 MHz up to 240 MHz when performance optimizing compile options were used. We obtained similar results attacking the power traces simulated for the ASIC. Despite the significant differences of the here investigated technologies the designs’ resistance against the attacks performed is similar: only a few points in the traces represent strong leakage sources allowing to reveal the key at very low and very high frequencies. For the “middle” frequencies the number of points which allow to successfully reveal the key increases when increasing the frequency.

Design of Angle based 27-level Trinary Ladder Inverter Using Cross Compiler

This paper presents the design of the Multi-Level Inverter circuit based on the switched ladder topology using the angle events for the level changes. The change of events for the inverter is formulated using the Half Height Algorithm. The VHDL code is utilized for the generation of the angles as digital equivalence with the resolution of 27 bits. In ladder topology, there are several types of inverter namely Binary Ladder Inverter, Ye Progression, Luo Progression. Among all these topologies, the Trinary Ladder topology is advantageous for the number of levels attainment with the less number of switches. Also, the carrier-based modulation is erroneous with the High THD% and low Voltage Parameter values. The use of the non-carrier half-height method manipulates the accurate angle to measure acceptable THD %. The proposed Trinary Switched Ladder Inverter is cross-compiled with Xilinx Vivado and Matlab Simulink Took to evaluate the parameters such as THD%, VRMS, VPEAK, for the 27-level. The parametric analysis exhibits improvement in the proposed Ladder topology with cost, size, and performance when synthesized using the Xilinx Vivado tool.

Design of Digital Operational Units with Low Power Consumption

The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power con­sumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.

Analysis of the Practical Implementation of Flicker Measurement Coprocessor for AMI Meters

Monitoring power quality (PQ) indicators is an important part of modern power grids’ maintenance. Among different PQ indicators, flicker severity coefficients Pst and Plt are measures of voltage fluctuations. In state-of-the-art PQ measuring devices, the flicker measurement channel is usually implemented as a dedicated processor subsystem. Implementation of the IEC 61000-4-15 compliant flicker measurement algorithm requires a significant amount of computational power. In typical PQ analysers, the flicker measurement is usually implemented as a part of the meter’s algorithm performed by the main processor. This paper considers the implementation of the flicker measurement as an FPGA module to offload the processor subsystem or operate as an IP core in FPGA-based system-on-chip units. The measurement algorithm is developed and validated as a Simulink diagram, which is then converted to a fixed-point representation. Parts of the diagram are applied for automatic VHDL code generation, and the classifier block is implemented as a local soft-processor system. A simple eight-bit processor operates within the flicker measurement coprocessor and performs statistical operations. Finally, an IP module is created that can be considered as a flicker coprocessor module. When using the coprocessor, the main processor’s only role is to trigger the coprocessor and read the results, while the coprocessor independently calculates the flicker coefficients.

I-DMAC: An Intelligent DMA Controller for Utilization - Aware Video Streaming used in AI Applications

The interpretation of large data streams necessitates high-performance repeated transfers, which overload Microprocessor System on Chips (SoC). The effective direct memory access (DMA) controller performs bulk data transfers without the CPU's involvement. The Direct Memory Controller (DMAC) solves this by facilitating bulk data transfer and execution. In this work, we created an intelligent DMAC (I-DMAC) for accessing video processing data without using CPUs. The model includes Bus selection Module, User control signal, Status Register, DMA supported Address, and AXI-PCI subsystems for improved video frame analysis. These modules are experimentally verified in Xilinx FPGA SoC architecture using VHDL code simulation and results compared to the E-DMAC model.

Generating Cipher Text using BLOWFISH Algorithm for Secured Data Communications

Cryptography plays a major role in the network security. In order to secure the data one must do encryption of the original message. In this paper, the design and analysis of high speed and high performance BLOWFISH algorithm is implemented in VHDL coding and compared with AES (Advanced Encryption Standard) algorithm. The BLOWFISH algorithm involves the process of giving the data and key as input to the encryption block. BLOWFISH encryption algorithm is designed and programmed in VHDL coding. Then it is implemented in Xilinx 10.1. This research is carried in the following steps: designing of encryption algorithm, writing VHDL code, simulating the code on “ModelSim altera 6.5e”, synthesizing and implementing the code using Xilinx’s ISE 10.1.This research aims in developing flexible and technology independent architectures in the areas of VPN software, file compression, public domain software such as smart cards, etc. Also presents the comparison of BLOWFISH and AES algorithms. Experimental results show that BLOWFISH algorithm runs faster than AES algorithm while both of them consume almost the same Power.

Design and Implementation of Reduced Power Energy Efficient Binary Coded Decimal Adder

<p>This paper presents a novel architecture for low power energy binary represented decimal addition. The proposed BCD adder uses Binary to Excess Six Converter (BESC) block for constant correction to adjusts binary outputs exceeding 9 to correct decimal values and exploits the inherent advantage of reduced delay and switching, due to elimination of long carry propagation in second stage addition as in conventional design and switching OFF of the BESC block for decimal outputs less than 9. The proposed BESC-BCD adder has been designed using VHDL code and synthesized using Altera Quartus II. Experimental results demonstrates that the proposed decimal adder can lead to significant power savings and delay reduction compared to existing BCD adders which is realised in better power-delay product(PDP) performance. For example the PDP saving of the proposed BESC-BCD adder for a 1 digit and 2 digit addition implementations are 11.6% and 16.05% respectively, compared to the best of the designs used for comparison.</p>

A Fast Approach for Generating Efficient Parsers on FPGAs

The development of modern networking requires that high-performance network processors be designed quickly and efficiently to support new protocols. As a very important part of the processor, the parser parses the headers of the packets—this is the precondition for further processing and finally forwarding these packets. This paper presents a framework designed to transform P4 programs to VHDL and to generate parsers on Field Programmable Gate Arrays (FPGAs). The framework includes a pipeline-based hardware architecture and a back-end compiler. The hardware architecture comprises many components with varying functionality, each of which has its own optimized VHDL template. By using the output of a standard frontend P4 compiler, our proposed compiler extracts the parameters and relationships from within the used components, which can then be mapped to corresponding templates by configuring, optimizing, and instantiating them. Finally, these templates are connected to output VHDL code. When a prototype of this framework is implemented and evaluated, the results demonstrate that the throughputs of the generated parsers achieve nearly 320 Gbps at a clock rate of around 300 MHz. Compared with state-of-the-art solutions, our proposed parsers achieve an average of twice the throughput when similar amounts of resources are being used.