Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
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Published By IEEE Comput. Soc. Press

0818675454

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Yield-performance tradeoffs for VLSI processors with partially good two-level on-chip caches

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1996.571989 ◽

2002 ◽

Cited By ~ 1

Author(s):

D. Nikolos ◽

H.T. Verges ◽

A. Vazaios ◽

S. Voulgaris

Keyword(s):

Yield Performance ◽

On Chip

Error identification and data retrieval in signature analysis based data compaction

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1996.572023 ◽

2002 ◽

Author(s):

Xiaoling Sun ◽

W. Tutak

Keyword(s):

Data Retrieval ◽

Signature Analysis ◽

Error Identification ◽

Data Compaction

Fault-tolerant shuffle-exchange and de Bruijn networks capable of quick broadcasting

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1996.572029 ◽

2002 ◽

Cited By ~ 2

Author(s):

N. Tsuda

Keyword(s):

Fault Tolerant ◽

De Bruijn

Fault detection and fault tolerance issues at CMOS level through AUED encoding

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1996.572032 ◽

2002 ◽

Cited By ~ 2

Author(s):

C. Bolchini ◽

G. Buonanno ◽

D. Sciuto ◽

R. Stefanelli

Keyword(s):

Fault Tolerance ◽

Fault Detection

Optimising high-level synthesis for self-checking arithmetic circuits

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1996.572033 ◽

2002 ◽

Cited By ~ 8

Author(s):

A. Antola ◽

V. Piuri ◽

M. Sami

Keyword(s):

Arithmetic Circuits ◽

High Level Synthesis ◽

High Level

Integration of DFM techniques and design automation

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1996.571991 ◽

2002 ◽

Cited By ~ 4

Author(s):

T.G. Waring ◽

G.A. Allan ◽

A.I. Walton

Keyword(s):

Design Automation

Tree checkers for applications with low power-delay requirements

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1996.572027 ◽

2002 ◽

Cited By ~ 3

Author(s):

C. Metra ◽

M. Favalli ◽

B. Ricco

Keyword(s):

Low Power

Test sequence generation for realistic faults in CMOS ICs based on standard cell library

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1996.572009 ◽

2002 ◽

Author(s):

Peilin Song ◽

Jien-Chung Lo

Keyword(s):

Test Sequence ◽

Standard Cell ◽

Standard Cell Library ◽

Cell Library ◽

Sequence Generation ◽

Test Sequence Generation

Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1996.572041 ◽

2002 ◽

Author(s):

T. Horita ◽

I. Takanami

Making defect avoidance nearly invisible to the user in wafer scale field programmable gate arrays

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1996.571980 ◽

2002 ◽

Cited By ~ 3

Author(s):

G.H. Chapman ◽

B. Dufort

Keyword(s):

Field Programmable Gate Arrays ◽

Wafer Scale ◽

Gate Arrays ◽

Scale Field ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Defect Avoidance

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI SystemsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

Yield-performance tradeoffs for VLSI processors with partially good two-level on-chip caches

Error identification and data retrieval in signature analysis based data compaction

Fault-tolerant shuffle-exchange and de Bruijn networks capable of quick broadcasting

Fault detection and fault tolerance issues at CMOS level through AUED encoding

Optimising high-level synthesis for self-checking arithmetic circuits

Integration of DFM techniques and design automation

Tree checkers for applications with low power-delay requirements

Test sequence generation for realistic faults in CMOS ICs based on standard cell library

Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults

Making defect avoidance nearly invisible to the user in wafer scale field programmable gate arrays

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Latest Publications