Logical gates recognition in a flat transistor circuit

O b j e c t i v e s. With the increasing complexity of verification and simulation of modern VLSI, containing hundreds of millions of transistors, the means of extracting the hierarchical description at the level of logical elements froma flat description of circuits at the transistor level are becoming the main tools for computer-aided design and verification. Decompilation tools for transistor circuits can not only significantly reduce the time to perform VLSI topology check, but also provide the basis for generating test cases, logical reengineering of integrated circuits and reverse engineering to detect untrusted attachments.The objective of the work is to solve the problem of extracting the structure of the functional level from a flat circuit of the transistor level by recognizing in it subcircuits that implement logical elements.M e t h o d s. Graph based methods are proposed for solving some key problems arising at the stage of structural recognition of CMOS gates in a transistor circuit: partitioning a graph into connectivity components corresponding to transistor subcircuits; recognition of subcircuits that are logical elements, and functions implemented by them; forming a library of recognized gates and constructing two-level transistor circuit. The original flat and resulting two-level transistor circuits are presented in SPICE format.Re s u l t s. The proposed methods are implemented in C++ as a part of a transistor circuit decompilation programfor the case without any predetermined cell library. All steps of the proposed methods of structural CMOS gates recognition are performed in a linear time from the number of transistors in the initial circuit.Co n c l u s i o n. The decompilation program has been tested on practical transistor-level circuits. Experiments indicate that the present tool is fast enough to process circuits with more than a hundred thousand transistors in a few minutes on a personal computer. Currently, the authors are developing methods for recognizing more complex elements in a transistor circuit, such as memory elements.

An efficient scRNA-seq dropout imputation method using graph attention network

Background Single-cell sequencing technology can address the amount of single-cell library data at the same time and display the heterogeneity of different cells. However, analyzing single-cell data is a computationally challenging problem. Because there are low counts in the gene expression region, it has a high chance of recognizing the non-zero entity as zero, which are called dropout events. At present, the mainstream dropout imputation methods cannot effectively recover the true expression of cells from dropout noise such as DCA, MAGIC, scVI, scImpute and SAVER. Results In this paper, we propose an autoencoder structure network, named GNNImpute. GNNImpute uses graph attention convolution to aggregate multi-level similar cell information and implements convolution operations on non-Euclidean space on scRNA-seq data. Distinct from current imputation tools, GNNImpute can accurately and effectively impute the dropout and reduce dropout noise. We use mean square error (MSE), mean absolute error (MAE), Pearson correlation coefficient (PCC) and Cosine similarity (CS) to measure the performance of different methods with GNNImpute. We analyze four real datasets, and our results show that the GNNImpute achieves 3.0130 MSE, 0.6781 MAE, 0.9073 PCC and 0.9134 CS. Furthermore, we use Adjusted rand index (ARI) and Normalized mutual information (NMI) to measure the clustering effect. The GNNImpute achieves 0.8199 (ARI) and 0.8368 (NMI), respectively. Conclusions In this investigation, we propose a single-cell dropout imputation method (GNNImpute), which effectively utilizes shared information for imputing the dropout of scRNA-seq data. We test it with different real datasets and evaluate its effectiveness in MSE, MAE, PCC and CS. The results show that graph attention convolution and autoencoder structure have great potential in single-cell dropout imputation.

Automatic FPGA Placement Configuration for Customer Designs

Searching for new ways to improve the efficiency of integrated circuits (IC) led to the development of specialized heterogeneous configurable IC (FPGA) and systems-on-a-chip. Their key feature is an extended interpretation of standard cell library, containing ready-to-use IP cores along with standard cells. Specific customer designs require the flexibility of the configurable heterogeneous IC’s architecture and, therefore, automatic CAD clustering and placement algorithms configuration. The development of efficient configuration methods and algorithms is impossible without relying on the mathematical apparatus. In this work, such mathematical apparatus is provided. The authors described a set-theoretic model of a hierarchical project and formalized the hierarchical approach to the netlist, using the apparatus of mathematical logic, set and graph theories. The correspondence between the customers designs’ elements and FPGA’s elements has been formalized to provide fast clustering and placement configuration. The obtained results provide the basis for future efficient methods for automatic placement and clustering configuration.

Gate-Level Static Approximate Adders: A Comparative Analysis

Approximate or inaccurate addition is found to be viable for practical applications which have an inherent error tolerance. Approximate addition is realized using an approximate adder, and many approximate adder designs have been put forward in the literature targeting an acceptable trade-off between quality of results and savings in design metrics compared to the accurate adder. Approximate adders can be classified into three categories as: (a) suitable for FPGA implementation, (b) suitable for ASIC type implementation, and (c) suitable for FPGA and ASIC type implementations. Among these, approximate adders, which are suitable for FPGA and ASIC type implementations are particularly interesting given their versatility and they are typically designed at the gate level. Depending on the way approximation is built into an approximate adder, approximate adders can be classified into two kinds as static approximate adders and dynamic approximate adders. This paper compares and analyzes static approximate adders which are suitable for both FPGA and ASIC type implementations. We consider many static approximate adders and evaluate their performance for a digital image processing application using standard figures of merit such as peak signal to noise ratio and structural similarity index metric. We provide the error metrics of approximate adders, and the design metrics of accurate and approximate adders corresponding to FPGA and ASIC type implementations. For the FPGA implementation, we considered a Xilinx Artix-7 FPGA, and for an ASIC type implementation, we considered a 32/28 nm CMOS standard digital cell library. While the inferences from this work could serve as a useful reference to determine an optimum static approximate adder for a practical application, in particular, we found approximate adders HOAANED, HERLOA and M-HERLOA to be preferable.

A Solution to Design Semi-static Null Convention Logic Cell Libraries

The Null Convention Logic (NCL) based asynchronous circuits have eliminated the disadvantages of the synchronous circuits, including noise, glitches, clock skew, power, and electromagnetic interference. However, using NCL based asynchronous designs was not easy for students and researchers because of the lack of standard NCL cell libraries. This paper proposes a solution to design a semi-static NCL cell library used to synthesize NCL based asynchronous designs. This solution will help researchers save time and effort to approach a new method. In this work, NCL cells are designed based on the Process Design Kit 45nm technology. They are simulated at the different corners with the Ocean script and Electronic Design Automation (EDA) environment to extract the timing models and the power models. These models are used to generate a *.lib file, which is converted to a *.db file by the Design Compiler tool to form a complete library of 27 cells. In addition, we synthesize the NCL based full adders to illustrate the success of the proposed library and compare our synthesis results with the results of the other authors. The comparison results indicate that power and delay are improved significantly.

Low-Latency Hardware Implementation of High-Precision Hyperbolic Functions sinhx and coshx Based on Improved CORDIC Algorithm

CORDIC algorithm is used for low-cost hardware implementation to calculate transcendental functions. This paper proposes a low-latency high-precision architecture for the computation of hyperbolic functions sinhx and coshx based on an improved CORDIC algorithm, that is, the QH-CORDIC. The principle, structure, and range of convergence of the QH-CORDIC are discussed, and the hardware circuit architecture of functions sinhx and coshx using the QH-CORDIC is plotted in this paper. The proposed architecture is implemented using an FPGA device, showing that it has 75% and 50% latency overhead over the two latest prior works. In the synthesis using TSMC 65 nm standard cell library, ASIC implementation results show that the proposed architecture is also superior to the two latest prior works in terms of total time (latency × period), ATP (area × total time), total energy (power × total time), energy efficiency (total energy/efficient bits), and area efficiency (efficient bits/area/total time). Comparison of related works indicates that it is much more favorable for the proposed architecture to perform high-precision floating-point computations on functions sinhx and coshx than the LUT method, stochastic computing, and other CORDIC algorithms.

A framework for evaluating edited cell libraries created by massively parallel genome engineering

Genome engineering methodologies are transforming biological research and discovery. Approaches based on CRISPR technology have been broadly adopted and there is growing interest in the generation of massively parallel edited cell libraries. Comparing the libraries generated by these varying approaches is challenging and researchers lack a common framework for defining and assessing the characteristics of these libraries. Here we describe a framework for evaluating massively parallel libraries of edited genomes based on established methods for sampling complex populations. We define specific attributes and metrics that are informative for describing a complex cell library and provide examples for estimating these values. We also connect this analysis to generic phenotyping approaches, using either pooled (typically via a selection assay) or isolate (often referred to as screening) phenotyping approaches. We approach this from the context of creating massively parallel, precisely edited libraries with one edit per cell, though the approach holds for other types of modifications, including libraries containing multiple edits per cell (combinatorial editing). This framework is a critical component for evaluating and comparing new technologies as well as understanding how a massively parallel edited cell library will perform in a given phenotyping approach.