System Level Design from HW/SW to Memory for Embedded Systems - IFIP Advances in Information and Communication Technology
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9783319900223, 9783319900230

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Integration of Robot Operating System and Ptolemy for Design of Real-Time Multi-robots Environments

System Level Design from HW/SW to Memory for Embedded Systems - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-319-90023-0_4 ◽

2017 ◽

pp. 38-47

Author(s):

Luis Feliphe Silva Costa ◽

Alisson V. Brito ◽

Tiago P. Nascimento ◽

Thiago Henrique Menezes Bezerra

Keyword(s):

Operating System ◽

Real Time ◽

Robot Operating System

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Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays

System Level Design from HW/SW to Memory for Embedded Systems - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-319-90023-0_18 ◽

2017 ◽

pp. 218-229

Author(s):

Éricles Sousa ◽

Frank Hannig ◽

Jürgen Teich

Keyword(s):

Coarse Grained ◽

Reconfigurable Arrays

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Low Latency FPGA Implementation of Izhikevich-Neuron Model

System Level Design from HW/SW to Memory for Embedded Systems - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-319-90023-0_17 ◽

2017 ◽

pp. 210-217 ◽

Cited By ~ 1

Author(s):

Vitor Bandeira ◽

Vivianne L. Costa ◽

Guilherme Bontorin ◽

Ricardo A. L. Reis

Keyword(s):

Neuron Model ◽

Fpga Implementation ◽

Low Latency ◽

Izhikevich Neuron Model

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Modeling and Analysis of SLDL-Captured NoC Abstractions

System Level Design from HW/SW to Memory for Embedded Systems - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-319-90023-0_11 ◽

2017 ◽

pp. 128-141

Author(s):

Ran Hao ◽

Nasibeh Teimouri ◽

Kasra Moazzemi ◽

Gunar Schirner

Keyword(s):

Modeling And Analysis

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Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs

System Level Design from HW/SW to Memory for Embedded Systems - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-319-90023-0_10 ◽

2017 ◽

pp. 116-127

Author(s):

Andrés Goens ◽

Jeronimo Castrillon

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Bit-Precise Formal Verification for SystemC Using Satisfiability Modulo Theories Solving

System Level Design from HW/SW to Memory for Embedded Systems - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-319-90023-0_5 ◽

2017 ◽

pp. 51-63

Author(s):

Lydia Jaß ◽

Paula Herber

Keyword(s):

Formal Verification ◽

Satisfiability Modulo Theories

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Rapid, High-Level Performance Estimation for DSE Using Calibrated Weight Tables

System Level Design from HW/SW to Memory for Embedded Systems - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-319-90023-0_16 ◽

2017 ◽

pp. 197-209

Author(s):

Kasra Moazzemi ◽

Smit Patel ◽

Shen Feng ◽

Gunar Schirner

Keyword(s):

Performance Estimation ◽

High Level ◽

Level Performance

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Combining an Iterative State-Based Timing Analysis with a Refinement Checking Technique

System Level Design from HW/SW to Memory for Embedded Systems - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-319-90023-0_8 ◽

2017 ◽

pp. 88-99

Author(s):

Tayfun Gezgin ◽

Björn Koopmann ◽

Achim Rettberg

Keyword(s):

Timing Analysis ◽

Refinement Checking

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Combining Service-Oriented Computing with Embedded Systems - A Robotics Case Study

System Level Design from HW/SW to Memory for Embedded Systems - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-319-90023-0_3 ◽

2017 ◽

pp. 27-37

Author(s):

Alexander Jungmann ◽

Jan Jatzkowski ◽

Bernd Kleinjohann

Keyword(s):

Embedded Systems ◽

Service Oriented Computing ◽

Service Oriented

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Taming the Memory Demand Complexity of Adaptive Vision Algorithms

System Level Design from HW/SW to Memory for Embedded Systems - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-319-90023-0_12 ◽

2017 ◽

pp. 145-158

Author(s):

Majid Sabbagh ◽

Hamed Tabkhi ◽

Gunar Schirner

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System Level Design from HW/SW to Memory for Embedded Systems - IFIP Advances in Information and Communication TechnologyLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer International Publishing

Integration of Robot Operating System and Ptolemy for Design of Real-Time Multi-robots Environments

Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays

Low Latency FPGA Implementation of Izhikevich-Neuron Model

Modeling and Analysis of SLDL-Captured NoC Abstractions

Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs

Bit-Precise Formal Verification for SystemC Using Satisfiability Modulo Theories Solving

Rapid, High-Level Performance Estimation for DSE Using Calibrated Weight Tables

Combining an Iterative State-Based Timing Analysis with a Refinement Checking Technique

Combining Service-Oriented Computing with Embedded Systems - A Robotics Case Study

Taming the Memory Demand Complexity of Adaptive Vision Algorithms

System Level Design from HW/SW to Memory for Embedded Systems - IFIP Advances in Information and Communication Technology
Latest Publications