scholarly journals Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays

2017 ◽  
pp. 218-229
Author(s):  
Éricles Sousa ◽  
Frank Hannig ◽  
Jürgen Teich
Keyword(s):  
Coarse Grained ◽  
Reconfigurable Arrays

scholarly journals UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment

2021 ◽  
Author(s):  
Dennis Wolf ◽  
Andreas Engel ◽  
Tajas Ruschke ◽  
Andreas Koch ◽  
Christian Hochberger
Keyword(s):  
Computing System ◽  
Coarse Grained ◽  
Instruction Level Parallelism ◽  
Control Engineering ◽  
Processing Elements ◽  
Actual Application ◽  
Reconfigurable Arrays ◽  
Engineering Environment ◽  
On Chip ◽  
Level Parallelism

AbstractCoarse Grained Reconfigurable Arrays (CGRAs) or Architectures are a concept for hardware accelerators based on the idea of distributing workload over Processing Elements. These processors exploit instruction level parallelism, while being energy efficient due to their simplistic internal structure. However, the incorporation into a complete computing system raises severe challenges at the hardware and software level. This article evaluates a CGRA integrated into a control engineering environment targeting a Xilinx Zynq System on Chip (SoC) in detail. Besides the actual application execution performance, the practicability of the configuration toolchain is validated. Challenges of the real-world integration are discussed and practical insights are highlighted.

Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays

2008 ◽  
Vol 43 (7) ◽  
pp. 151-160 ◽  
Author(s):  
Bjorn De Sutter ◽  
Paul Coene ◽  
Tom Vander Aa ◽  
Bingfeng Mei
Keyword(s):  
Register Allocation ◽  
Coarse Grained ◽  
Reconfigurable Arrays ◽  
Placement And Routing

Double-Pumping the Interconnect for Area Reduction in Coarse-Grained Reconfigurable Arrays

2021 ◽  
Author(s):  
Xinyuan Wang ◽  
Tianyi Yu ◽  
Hsuan Hsiao ◽  
Jason Anderson
Keyword(s):  
Coarse Grained ◽  
Area Reduction ◽  
Reconfigurable Arrays

scholarly journals Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks

2011 ◽  
Vol 57 (8) ◽  
pp. 761-777 ◽  
Author(s):  
Ricardo S. Ferreira ◽  
João M.P. Cardoso ◽  
Alex Damiany ◽  
Julio Vendramini ◽  
Tiago Teixeira
Keyword(s):  
Coarse Grained ◽  
Reconfigurable Arrays ◽  
Placement And Routing ◽  
Fast Placement

scholarly journals Low-Complexity Online Synthesis for AMIDAR Processors

2010 ◽  
Vol 2010 ◽  
pp. 1-15 ◽  
Author(s):  
Stefan Döbrich ◽  
Christian Hochberger
Keyword(s):  
Expert Knowledge ◽  
Low Complexity ◽  
Coarse Grained ◽  
Strong Impact ◽  
Reconfigurable Logic ◽  
Gate Arrays ◽  
Reconfigurable Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Synthesis Approach

Future chip technologies will change the way we deal with hardware design. First of all, logic resources will be available in vast amount. Furthermore, engineering specialized designs for particular applications will no longer be the general approach as the nonrecurring expenses will grow tremendously. Reconfigurable logic has often been promoted as a solution to these problems. Today, it can be found in two varieties: field programmable gate arrays or coarse-grained reconfigurable arrays. Using this type of technology typically requires a lot of expert knowledge, which is not sufficiently available. Thus, we believe that online synthesis that takes place during the execution of an application is one way to broaden the applicability of reconfigurable architectures. In this paper, we show that even a relative simplistic synthesis approach with low computational complexity can have a strong impact on the performance of compute intensive applications.

Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array

2015 ◽  
Vol 24 (03) ◽  
pp. 1550043 ◽  
Author(s):  
Chen Yang ◽  
Leibo Liu ◽  
Yansheng Wang ◽  
Shouyi Yin ◽  
Peng Cao ◽  
...  
Keyword(s):  
Input Data ◽  
Multimedia System ◽  
Coarse Grained ◽  
Reconfigurable Processor ◽  
Decoding Algorithms ◽  
High Profile ◽  
Context Switching ◽  
Reconfigurable Arrays ◽  
Reconfigurable Array ◽  
Major Bottleneck

The major bottleneck of coarse-grained reconfigurable arrays (CGRAs) is the excessive configuration overhead; as a result, computing potential cannot be fully utilized. At run-time, the function of CGRAs can be fully and dynamically reconfigured by changing contexts. Therefore, the frequency of context switching on CGRAs is very high. On the other hand, the configuration time of CGRAs is very long. This paper proposes three configuration approaches to reduce interval latency when switching configuration contexts. These proposed approaches include input data relocation (IDR), line-based context switching (LCS), and loop interval minimization (LIM). IDR relocates input data to the first stage of the pipeline; as a result, the delay time for the input data of the next data flow graph (DFG) is reduced. LCS is a LCS mechanism for adjacent independent DFGs to reduce the interval of context switching, thereby expanding the depth of the pipeline. LIM is used to minimize the interval of loops. Simulations on a coarse-grained reconfigurable processor called reconfigurable multimedia system (REMUS) show that 1080 p@30 fps for H.264 high profile video decoding can be achieved under 200 MHz working frequency. As for AVS and MPEG2 decoding algorithms, much higher performance, i.e., 1080 p@39 fps and 1080 p@41 fps, can be achieved respectively.

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