Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)
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TOTAL DOCUMENTS

129

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Estimation of average switching power under accurate modeling of signal correlations

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143) ◽

10.1109/cicc.1998.695029 ◽

2002 ◽

Cited By ~ 1

Author(s):

Zhanping Chen ◽

K. Roy ◽

Yibin Ye

Keyword(s):

Switching Power

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CMOS technology characterization for analog and RF design

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143) ◽

10.1109/cicc.1998.694900 ◽

2002 ◽

Cited By ~ 3

Author(s):

B. Razavi

Keyword(s):

Cmos Technology ◽

Rf Design

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MDSP-II: 16-bit DSP with mobile communication accelerator

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143) ◽

10.1109/cicc.1998.694896 ◽

2002 ◽

Cited By ~ 3

Author(s):

B.W. Kim ◽

J.H. Lang ◽

Y.S. Kwon ◽

K.M. Lee ◽

I.H. Kim ◽

...

Keyword(s):

Mobile Communication

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A multistage amplifier topology with embedded tracking compensation

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143) ◽

10.1109/cicc.1998.694999 ◽

2002 ◽

Cited By ~ 2

Author(s):

R.M. Ziazadeh ◽

Hiok-Tiaq Ng ◽

D.J. Allstot

Keyword(s):

Multistage Amplifier

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A 2 V 1.6 GHz BJT phase-locked loop

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143) ◽

10.1109/cicc.1998.695041 ◽

2002 ◽

Cited By ~ 3

Author(s):

Wei-Zen Chen ◽

Jieh-Tsorng Wu

Keyword(s):

Phase Locked Loop

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A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143) ◽

10.1109/cicc.1998.694929 ◽

2002 ◽

Cited By ~ 3

Author(s):

A. Hanami ◽

S. Scotzniovsky ◽

K. Ishihara ◽

T. Matsumura ◽

S. Takeuchi ◽

...

Keyword(s):

Motion Estimation ◽

Video Encoding ◽

High Quality ◽

Array Architecture ◽

Quality Video ◽

High Quality Video

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Re-inventing the DRAM for embedded use: a compiled, wide-databus DRAM macrocell with high bandwidth and low power

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143) ◽

10.1109/cicc.1998.694981 ◽

2002 ◽

Author(s):

R.C. Foss ◽

J. Wu ◽

J. Benzreba ◽

G. Valcourt ◽

P. Vlasenko ◽

...

Keyword(s):

Low Power ◽

High Bandwidth

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Transforming small-signal modeling into control system modeling

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143) ◽

10.1109/cicc.1998.695020 ◽

2002 ◽

Author(s):

F. Leyn ◽

W. Sansen ◽

G. Gielen

Keyword(s):

Control System ◽

System Modeling ◽

Small Signal ◽

Signal Modeling ◽

Small Signal Modeling

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A low-power 16-bit multiplier-accumulator using series-regulated mixed swing techniques

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143) ◽

10.1109/cicc.1998.695027 ◽

2002 ◽

Cited By ~ 5

Author(s):

R.K. Krishnamurthy ◽

H. Schmit ◽

L.R. Carley

Keyword(s):

Low Power

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A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143) ◽

10.1109/cicc.1998.694977 ◽

2002 ◽

Cited By ~ 1

Author(s):

D. Reese ◽

E. Chun ◽

S. Cheung ◽

E. Lau ◽

M. Chu ◽

...

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Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Estimation of average switching power under accurate modeling of signal correlations

CMOS technology characterization for analog and RF design

MDSP-II: 16-bit DSP with mobile communication accelerator

A multistage amplifier topology with embedded tracking compensation

A 2 V 1.6 GHz BJT phase-locked loop

A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications

Re-inventing the DRAM for embedded use: a compiled, wide-databus DRAM macrocell with high bandwidth and low power

Transforming small-signal modeling into control system modeling

A low-power 16-bit multiplier-accumulator using series-regulated mixed swing techniques

A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)
Latest Publications