1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)
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The TANGRAM co-processor for MPEG-4 visual compositing

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) ◽

10.1109/sips.1999.822336 ◽

2003 ◽

Cited By ~ 3

Author(s):

M. Berekovic ◽

T. Selinger ◽

C. Miro ◽

G. Ghigo ◽

C. Heer ◽

...

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A 2 way VLIW processor architecture for embedded multimedia applications

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) ◽

10.1109/sips.1999.822326 ◽

2003 ◽

Cited By ~ 1

Author(s):

Jiyang Kang ◽

Jae-Woo Ahn ◽

Jiyoung Cho ◽

Ki-Il Kum ◽

Wonyong Sung

Keyword(s):

Multimedia Applications ◽

Processor Architecture ◽

Vliw Processor

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A high-speed CORDIC algorithm and architecture for DSP applications

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) ◽

10.1109/sips.1999.822381 ◽

2003 ◽

Cited By ~ 9

Author(s):

M. Kuhlmann ◽

K.K. Parhi

Keyword(s):

High Speed ◽

Cordic Algorithm ◽

Dsp Applications

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A high throughput rate and low circuit complexity QAM channel equalizer design based on bit serial scheme

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) ◽

10.1109/sips.1999.822362 ◽

2003 ◽

Author(s):

Yin-Tsung Hwang ◽

Wei-Cheng Lin

Keyword(s):

High Throughput ◽

Circuit Complexity ◽

Throughput Rate ◽

Bit Serial

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A novel hardware algorithm for residue evaluation

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) ◽

10.1109/sips.1999.822374 ◽

2003 ◽

Cited By ~ 1

Author(s):

K. Karagianni ◽

T. Stouraitis

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Symmetric and programmable multi-chip module for rapid prototyping system

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) ◽

10.1109/sips.1999.822335 ◽

2003 ◽

Cited By ~ 1

Author(s):

Mao-Hsu Yen ◽

Sao-Jie Chen ◽

S.H. Lan

Keyword(s):

Rapid Prototyping ◽

Rapid Prototyping System

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Peak-error-constrained optimal shape representation

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) ◽

10.1109/sips.1999.822338 ◽

2003 ◽

Author(s):

Leu-Shing Lau

Keyword(s):

Shape Representation ◽

Optimal Shape

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A detailed analysis of MediaBench

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) ◽

10.1109/sips.1999.822350 ◽

2003 ◽

Cited By ~ 8

Author(s):

B. Bishop ◽

T.P. Kelliher ◽

M.J. Irwin

Keyword(s):

Detailed Analysis

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A novel VLSI architecture for a variable-length key, 64-bit Blowfish block cipher

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) ◽

10.1109/sips.1999.822363 ◽

2003 ◽

Author(s):

Yeong-Kang Lai ◽

Yu-Chuan Shu

Keyword(s):

Block Cipher ◽

Vlsi Architecture ◽

Variable Length

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A cost-effective design for MPEG2 audio decoder with embedded RISC core

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) ◽

10.1109/sips.1999.822341 ◽

2003 ◽

Author(s):

Tsung-Han Tsai ◽

Liang-Gee Chen ◽

Ren-Jr Wu

Keyword(s):

Cost Effective ◽

Audio Decoder ◽

Effective Design

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1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

The TANGRAM co-processor for MPEG-4 visual compositing

A 2 way VLIW processor architecture for embedded multimedia applications

A high-speed CORDIC algorithm and architecture for DSP applications

A high throughput rate and low circuit complexity QAM channel equalizer design based on bit serial scheme

A novel hardware algorithm for residue evaluation

Symmetric and programmable multi-chip module for rapid prototyping system

Peak-error-constrained optimal shape representation

A detailed analysis of MediaBench

A novel VLSI architecture for a variable-length key, 64-bit Blowfish block cipher

A cost-effective design for MPEG2 audio decoder with embedded RISC core

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)
Latest Publications